I have a very basic question about VHDL. Do we need a separate .ucf file for each .vhd file or not? The reason I am having many .vhd files because each of the entity specifies a different interface. Should I combine all of them? For example, I am working on SPI interface of the FPGA to configure a chip, and LVDS interface of the FPGA to read output from the chip (just for higher data rate). Therefore, right now, I am having 2 .vhd files for each interface. Is that correct? Any recommendation on which document to read would be appreciated. Thank you.
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1Normally you would have one top level VHDL file for your FPGA, which instantiates the others (SPI, LVDS interfaces) as components and connects them to its ports. Then, one UCF for that file. – Jan 09 '18 at 17:38
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@BrianDrummond Thank you. So I can have SPI and LVDS interfaces in the same entity?? – Lac Jan 09 '18 at 17:46
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All components are usually integrated into a single top level entity. It would be the final "wrapper" VHDL file which defines all ports, generics and all of the entire design. This is the HDL file which is then synthesized. So one UCF file is enough, which is defined only for this top level module.
You can refer to synthesis guides from Altera or Xilinx website.
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Besides the listed reasons like the the other answers, the Xilinx guides do suggest multiple files. For the Altera the question is not valid, because SDC files do not support physical constraints. These are stored in a separate file anyway. – Paebbels Jan 11 '18 at 20:44
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From the Xilinx UG903, page 8 (note: this is Vivado not ISE but should still apply):
Xilinx recommends that you separate timing constraints and physical constraints by saving them into two distinct file s. You can also keep the constraints specific to a certain module in a separate file.
Typically, I will have a single project wide timing constraints file and a single physical constraints file. Then if I have any large components that I plan to reuse in other projects I will create individual timing constraint files for them.
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I would go one step further an declare one UCF file per physical interface. That allows you to quickly plug in and out parts of your design. So when you don't need the DDR3 interface, just disable the DDR3 constraint file. If you need a create just a physical memory test design, plugin the DDR3 constraints and the system clock constraints. If you have different development boards of similar FPGAs, create constraint files with the same naming scheme and you can switch from board to board with the same design in minutes! – Paebbels Jan 10 '18 at 10:42
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That's what e.g. the [PoC Library](https://github.com/VLSI-EDA/PoC) does by providing dozens of constraint files for well known boards. => [see constraint files](https://github.com/VLSI-EDA/PoC/tree/master/ucf) – Paebbels Jan 10 '18 at 10:42
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