7

This is the circuit I made:

schematic

simulate this circuit – Schematic created using CircuitLab

This simple circuit incorporates differential stage - VA (Voltage-amplification) stage - OPS (Output Power Stage). Open loop gain is high, closed loop gain is approx. the value of 10. Miller effect of VA stage is compensated via Cc, which makes local feedback. Q4 is used for biasing of the OPS - when Vce = 2.4V, the current through Q6 and Q8 should be approx. 10 mA and the current through Q5 and Q7 should be approx. C1 is used for AC to bypass Q4 to be fed into base of Q7. 1 mA. Global NFB (Negative Feedback) is taken from the output and brought back to the non-inverting input of differential stage. I was first aiming for this amplifier to be loaded by 8 Ohm speaker but then changed my mind to 100 Ohm load, since there would be too high voltage gain drop (the current through last stage should be higher in my opinion). The current through Q3 and Q4 is approx. 10 mA, while collector currents through Q1 and Q2 are approx. 1 mA

Unloaded amplifier behaves as expected, but loaded amplifier has great amount of distortion in between its output signal. I cannot figure it out what is so wrong with this amplifier to produce such high amounts of distortion on the output.

This is the signal of unloaded amplifier versus loaded amplifier (5V per division):

enter image description here enter image description here

What is wrong here stays a mystery for me but maybe you can figure it out.

Here is a little proof for the circuit I just made: enter image description here

τεκ
  • 4,229
  • 1
  • 16
  • 17
Keno
  • 2,360
  • 2
  • 35
  • 65
  • 2
    Cripes, Keno! You are insanely busy at this stuff! My first comment, without looking at anything in detail, is that your output driver stage uses two quadrants of Darlingtons. Yuk! Use Sziklai, instead. And your VBE multiplier looks terribly wrongly arranged, just at a glance. – jonk Jan 06 '18 at 18:48
  • 7
    That's not distortion, that's oscillation. Somehow you have built an AM radio transmitter. If it's all on a breadboard I'm not surprised it's unstable, but it's not going to be easy to fix by guesswork. Start by decoupling the power rails though. –  Jan 06 '18 at 19:25
  • 1
    To start with, get rid of all of those ridiculous loops of jumper wire! No wonder it has enough parasitic feedback to oscillate! You should be able to lay this out on your breadboard so that 90% of the connections can be made using the component leads alone. – Dave Tweed Jan 06 '18 at 19:35
  • 1
    Yes definitely start by adding 100uF between +20V and ground/ground and -20V if you don't have it already. This should be more or less part of your standard breadboard setup. Here's what 1uH on the leads from the power supply (the self-inductance of 1m of wire) and 100pF of stray capacitance on the output could do: https://i.imgur.com/JrJwMI8.png – τεκ Jan 06 '18 at 19:39
  • Note that we discourage broad, open-ended design review questions here on EE.SE: The answer(s) tend to become long strings of unrelated edits and/or comments. While this might help you with your immediate problems, it is of no value to the site overall. We DO allow design review questions in which you explain your choices and then focus on a few points about which you still have doubts. To get a better feel of what is or is not acceptable, search for "design review" on the meta site. – Dave Tweed Jan 06 '18 at 19:39
  • 1
    Cables act as antennas. Your VAS stage does not contain a current source. The lack of CS may lead to instability (i.e. oscillation which is actually your problem rather than distortion). – Rohat Kılıç Jan 06 '18 at 20:38
  • @jonk Yuk!? What is so bad about Darlington configuration, unless it requires a larger supply for biasing two extra bases comparing to Sziklai pair? And what is wrong with Vbe multiplier? It does its function. – Keno Jan 06 '18 at 21:57
  • 1
    @Keno Have a look at this answer: [2 quadrant Sziklai design](https://electronics.stackexchange.com/questions/348485/is-there-a-good-topology-for-splitting-a-dc-power-supply-from-a-few-lm2576-and-l/348506#348506). I get into some details here and there in that answer, which bear on the question you just asked regarding Darlingtons. And your \$V_{BE}\$ isn't even wrong! It's way off from where it needs to be. No idea why others aren't making more of it. – jonk Jan 06 '18 at 22:01
  • @jonk What is wrong with Vbe now? Why don't you just tell me what is wrong with Vbe mulitplier and how should be arranged and what bothers you about Vbe itself? In short, of course, no need for answering, unless you really want, I wouldn't mind. – Keno Jan 06 '18 at 23:12
  • @jonk is right. Q4 was probably meant to be a [Vbe multiplier](https://en.wikipedia.org/wiki/Rubber_diode) but isn't. The circuit works anyway due to the magic that is negative feedback. – τεκ Jan 06 '18 at 23:15
  • @τεκ Yes, this is true. If I make Vce across Q4 approx. 0V, then the bases still conduct. But it still somehow affects on the output current of OPS - increasing Vce across Q4 increases Iq of OPS. – Keno Jan 06 '18 at 23:29
  • 2
    @Keno The goal of Q4 is to keep the base of Q5 about 4*Vbe above the base of Q7. The thing to do this is called a [Vbe multiplier](https://en.wikipedia.org/wiki/Rubber_diode). You don't have it set up right. – τεκ Jan 06 '18 at 23:43
  • 1
    @Keno Been busy elsewhere and only now an reading stuff again. I do have a life, sometimes. You've been focusing on a lot of details, so far, and I appreciate what that takes. It's no fault of yours that you haven't also acquired the Vbe multiplier yet. It's just another thingy you have to pull in and acquire, now. It isn't complex. But you didn't get the topology even close to right. But as τεκ writes, NFB cures many ills and is blinding you to the problem there. – jonk Jan 06 '18 at 23:52
  • 2
    @Keno I discuss in the link I gave, but a problem with Darlington here is that you are talking about ***four*** VBEs to compensate for the VBE multiplier (Q4). The Early Effect is a bigger problem at 4X rather than 2X (as temp varies) and the temperature compensation parabola (needs a collector resistor) is more difficult to get right, I think. Also, with Sziklai you only need to worry about the temperatures of the transistors driving the main power BJTs, which is much much less of a problem than dealing with temp changes of the main power BJTs themselves. – jonk Jan 06 '18 at 23:58
  • @DaveTweed No value to the site itself? Then why is this post getting upvotes for? – Keno Jan 07 '18 at 11:02
  • 1
    Because there are people who enjoy solving puzzles like this. But once you get the answer you need, all of this blather will not be any use to future visitors. Even if someone else has made the same mistakes that you have, they will have a hard time finding this question, and if they do, learning anything from it. – Dave Tweed Jan 07 '18 at 12:27
  • @DaveTweed You are basically saying that any question asked on EE.SE would be meaningless for this site and for readers that are unknown to EE.SE but visit this site for some answers they might find it helpful? – Keno Jan 07 '18 at 12:36
  • 1
    I have no idea what you just said. I'm not here to argue with you; I'm just here to enforce policies that have been established based on long experience. You have asked a long sequence of questions all related to this project, but you don't seem to be learning from them. The signal-to-noise ratio is extremely low, and that's what drags down the value to the site. – Dave Tweed Jan 07 '18 at 14:17
  • @DaveTweed I don't want to argue with you too, but how the heck do you know what I learned from all this? Because I am actively posting questions? What is wrong with that? – Keno Jan 07 '18 at 19:37

3 Answers3

4

I didn't really read the whole question (too long, and didn't get to a clear point fast enough), but this is not what you seem to mean by "distortion":

This is very clearly the amplifier oscillating on its own when given a little kick by the input signal.

A brief look at the schematic shows why this shouldn't be a surprise. There is no capacitance on the power rails at all! The output is loading the power rails, which changes their voltage a little. That small change is picked up by the input stage, and then amplified thru the rest of the amplifier.

To fix this:

  1. Put decent capacitance to ground on each power rail. This should be several 100 µF at least.

  2. Break the power rails to the left of Q5 for the positive, and the left of Q7 for the negative. Put a small resistor in series, then followed by another few 100 µF to ground. This time, though, add some high frequency bypassing too, something like 10 µF ceramic to ground on each power line.

I think I remember telling you this before, but I don't feel like digging around in old history right now.

I think you are also told before that Darlingtons are not a good idea here. They require higher drive voltage than output, and have rather high saturation voltage. There are better ways, like using a power PNP for the top pass element of the final stage, then a power NPN for the bottom. Those can be driven by smaller NPN and PNP transistors, respectively. However, that is beyond the scope of this question.

Olin Lathrop
  • 310,974
  • 36
  • 428
  • 915
3

What you are seeing is not distortion. It is the amplifier oscillating at high frequency because +20/-20V have no bulk capacitance. This makes it so they have high impedance at high frequency due to the inductance of the wires going to your power supply and the power supply's limited frequency response.

Here's a simulation:

1uH is approximately the inductance of 1 meter of wire. The 100pF attached to the output could come from the stray capacitance of the breadboard.

Also: I redrew your schematic in a way that's a little clearer.

schematic

simulate this circuit – Schematic created using CircuitLab

τεκ
  • 4,229
  • 1
  • 16
  • 17
  • 1
    You could edit the question and put the new schematic in there. – JRE Jan 06 '18 at 20:39
  • @JRE good idea. – τεκ Jan 06 '18 at 20:49
  • I added those caps as you commented. And the output signal waveform changed to more sine alike but still incorporating oscillation signal within it. Then I started to move those jumpers in random positions (not connections but jumper's part connecting one end to other) and also the output signal waveform was changing. At some point (with amplifier loaded) the distortion disappeared and sinusoidal waveform was seen on the output of amplifier. – Keno Jan 06 '18 at 23:18
  • 1
    @Keno You should observe the +20V and -20V with the oscilloscope. If they're not totally flat, add more capacitance. There's basically no such thing as too much. – τεκ Jan 06 '18 at 23:50
3

I just quickly drew this up, the last hour or so. I agree that with wires on a protoboard such as what you are using, it's important to have lots of bypass capacitance right on the protoboard itself. Include that. However, I think you may also have had problems due to the fact that there is lots of capacitance (a few pF) between each nearby hole on the protoboard, too. And you didn't add some capacitance on the feedback resistor (which may be needed.) The values here are designed around the idea that you can deliver perhaps as much as \$2\:\text{A}\$ peak into an \$8\:\Omega\$ load, so I tried to take that into account. That said, I've really not done anything here but just "pop this out," quickly and roughly. No time for more than that.

schematic

simulate this circuit – Schematic created using CircuitLab

Here I set up the Sziklai output driver arrangement with the added \$V_{BE}\$ multiplier present as it should be. I've used two variable resistors, one keeping your \$2\:\text{k}\Omega\$ value (which I guess you have) and another being \$100\:\Omega\$. \$P_1\$ lets you adjust the quiescent current (which you can measure by checking the voltage between the collectors of \$Q_{12}\$ and \$Q_{13}\$.) \$P_2\$ lets you adjust things for temperature and Early Effect compensation. But feel free to completely remove \$P_2\$ and \$R_3\$ by shorting them out, if you want to. They are NOT critical. Just an offering. If you do ignore (short) them, then you may need to pick a different value for \$R_2\$ (smaller, perhaps.) You'll know if that's needed when you find you can't adjust the quiescent current to the right range with \$P_1\$. If so, pick a nearby value for \$R_2\$ and try adjusting \$P_1\$ again.

Feel free to ask questions, Keno. I'll try and answer them as I'm able to. To others, feel free to criticize and kibbitz.

Shoot for a quiescent current (no input signal) of perhaps one milliamp, or so. Adjust \$P_1\$ for that and read it off as I mentioned above. You can work out the voltage you'd need to read. (Feel free to increase the values of \$R_{E_3}\$ and/or \$R_{E_4}\$ to make it easier to pick this out -- just don't drop more than few tenths of a volt while adjusting things there.)

Assuming you need lots of current gain (and you do) for the output driver section, the Sziklai arrangement has a few advantages over the Darlington arrangement:

  1. There are just two \$V_{BE}\$ drops to deal with.
  2. These two \$V_{BE}\$ drops are subject to far less heating, so their \$V_{BE}\$ drops are more stable making it easier to plan the \$V_{BE}\$ multiplier behavior.

In the Darlington case, while it is still true that two of the four BJTs have less heating taking place, the fact is that it includes all four \$V_{BE}\$ drops in what is required to be controlled via the \$V_{BE}\$ multiplier. So this compounds the design of the multiplier or else decreases thermal stability. Either way, it's not a good thing in favor of Darlington. So one usually doesn't use it for cases like this.

(In short, I don't know of a good reason to use Darlington, other than part availability issues perhaps. So, for example, if high current PNPs are horrible and/or unavailable, you might replace \$Q_{10}+Q_{12}\$ with a Darlington alternative using only NPN. But you'd still probably keep the Sziklai on the bottom quadrant of the driver.)

Let's look at the current source stripped of some of the "extras." (They aren't important to understand the basic DC operation.)

schematic

simulate this circuit

Ignoring whatever load there might be for the \$Q_5\$ collector, you should be able to very roughly sketch out in your mind that this circuit will actually bias itself in some fashion. From \$+20\:\text{V}\$, there is a DC path through \$RSET_1\$, the emitter of \$Q_5\$ to its base, then through \$R_{11}\$, which is tied to ground. So there is no question that there will be some active current through that path. If \$Q_6\$ were pulled from the circuit, and assuming that \$Q_5\$ had a collector load to ground (or \$-20\:\text{V}\$) which didn't otherwise cause \$Q_5\$ to saturate, then we could compute the base current as:

$$I_B=\frac{20\:\text{V}-V_{BE}}{R_{11}+\left(\beta+1\right)\cdot RSET_1}$$

And this would be little different from the standard CE amplifier computation.

But in this case there is an added \$Q_6\$. What does it do? Before it is added, there is no particular limit to the voltage drop across \$RSET_1\$. It could be several volts, or more. But with \$Q_6\$ added, which is sensitive to its base-emitter voltage, any voltage drop across \$RSET_1\$ that is larger than about one \$V_{BE}\$ will cause \$Q_6\$ to source lots more current through its collector, all of which must be driven to ground via \$R_{11}\$. This added current causes an increased voltage drop across \$R_{11}\$. (Keep in mind that by adding only a mere \$60\:\text{mV}\$ to the voltage drop across \$RSET_1\$, the collector of \$Q_6\$ will source ten times as much collector current into \$R_{11}\$ which will mean also 10 times the voltage drop across \$R_{11}\$!) This increased voltage drop across \$R_{11}\$ also means that the base of \$Q_5\$ is pushed upwards (towards the positive rail) and this causes \$Q_5\$'s \$V_{BE}\$ to get "pinched", thus reducing its collector current.

What exactly is \$Q_5\$'s collector current? Well, it pretty much is the current in \$RSET_1\$. That's about it. And since we are also pretty certain about the voltage across it (one \$V_{BE}\$), we can compute the collector current in \$Q_5\$ pretty reliably. \$Q_6\$ will be constantly and carefully monitoring its own \$V_{BE}\$ and responding immediately to any changes by adjusting things at \$Q_5\$'s base and "pushing on/sinking current into" \$R_{11}\$ to make those changes work in the right direction.

In the end, there are about two \$V_{BE}\$ drops from your positive rail down to the base of \$Q_5\$. It's collector can "reach" about that high towards the positive rail before it starts saturating (causing other problems.) And this gives quite a lot of compliance range for the collector of \$Q_5\$. Which is a good thing.

In this short-hand version of the circuit found at the beginning of my answer, I removed \$RB_1\$. It's not strictly required for explaining the circuit. But it is added to help with possible oscillation when the circuit is part of a larger system and there is an AC signal being amplified. It doesn't drop much voltage, so you can "mostly ignore it." In general, a resistor of a few hundred Ohms to perhaps a thousand Ohms does the job, but the better value to use does depend on the base current (of course.) It's just not particularly critical-valued.

jonk
  • 77,059
  • 6
  • 73
  • 185
  • Haven't got into details of you answer (I definitely will) but there is 150k base resistor for Q1 and Rf1 is 10k. Shouldn't they be of the same value for both of them so the base voltage is at approx. same level for both of Q1 and Q2? – Keno Jan 07 '18 at 10:57
  • And I don't know if incorporation of current mirror at the collectors of Q1 and Q2 is a good idea, since I didn't quite understood what exactly happens there last time we discussed about it? – Keno Jan 07 '18 at 11:00
  • Also, why is that 0.22 ohm output power resistor so famous for, since I saw it in almost every amplifier design, incorporating OPS? – Keno Jan 07 '18 at 12:52
  • But is the C_LOAD really needed? If the amplifier is a well-designed one, then between the point of RE3 and RE4, there should be approx. 0V of DC offset, so I don't know if that cap is really needed? – Keno Jan 07 '18 at 12:56
  • And the last thing, what is with that divider of R11 and R14 and a cap in between to ground? What's the function of that part of a circuit? – Keno Jan 07 '18 at 13:15
  • @Keno \$R_{in}\$ perhaps could be lower-valued. My mind was in a Darlington mode, but the circuit isn't. Feel free to reduce it by a factor of 10. Good catch. It doesn't have to be the same value as \$R_{f_1}\$ as this is an amplifier and there's a bypass cap at the output. But something in the vicinity isn't a bad idea. The current mirror *is* a good idea. I included it to get you moving in a better direction and to get you at least struggling to think more about why. – jonk Jan 07 '18 at 15:57
  • @Keno In this case, I estimated that \$I_{PEAK}\approx 2\:\textrm{A}\$ with your power supply rails. I want no more than perhaps \$\frac{1}{2}\:\textrm{V}\$ across the emitter resistors at that value. There are reasons (more than one), but that's a reasonable target when just shooting from the hip like this. The peak current and this voltage value directs the value of \$220\:\text{m}\Omega\$ for the output emitter resistors. – jonk Jan 07 '18 at 16:04
  • @Keno The output capacitor is probably a "slightly good" idea when building something for hobby use like this. If this were a professional system and you had the ability to carefully adjust the DC offset output without signal input, then I think the argument of losing it would be better made. In this case, it picks up and nulls any DC offset in the output, so it greatly reduces the need to tweak/calibrate the amplifier. Feel free to lose it and measure the offset voltage, though. Good lesson, I suspect. – jonk Jan 07 '18 at 16:07
  • @Keno \$R_{11}\$ and \$R_{14}\$ could just be replaced with their sum and you could lose the cap. Cutting it in half and putting a capacitor there is a kind of "bootstrapping" that is often used. Probably better left as another lesson for another day, though. Feel free to replace the three parts with just one resistor. – jonk Jan 07 '18 at 16:10
  • 1
    @Keno All good questions! – jonk Jan 07 '18 at 16:11
  • As the thing concerns of bootstrapping - I read your whole answer from this post, https://electronics.stackexchange.com/questions/268944/effect-of-bootstrapping-in-amplifier-circuit . The bootstrapping method doesn't look similar to the one from your circuit shown here but serves (probably) for same reason as there - to increase input impedance of input stage? – Keno Jan 07 '18 at 16:19
  • About the function of Q6. I think I saw that in my book (Audio Power Amplifier Design Handbook by Douglas Self) but I know I don't quite remember or get it now what is its purpose (next to the current source for diff-amp)? – Keno Jan 07 '18 at 16:25
  • @Keno In the split-resistor + capacitor case, I need a DC path for \$Q_6\$'s collector load, but splitting it up like this substantially increases the voltage gain of \$Q_6\$. (I also know that \$Q_7\$ is going to still be a little *annoying* with respect to its base current variations when an AC signal is present at the input. So perhaps some help here, too.) – jonk Jan 07 '18 at 17:26
  • @Keno We want a constant current source for the diff-pair. \$R_{11}+R_{14}\$ pull \$Q_5\$ active. As this happens, a voltage develops across \$RSET_1\$. As that voltage drop gets high enough, \$Q_6\$ becomes increasingly active and it's collector pulls very actively in a direction opposed to that of \$R_{11}+R_{14}\$ to bring it into a stable point of operation with a fixed \$V_{BE}\$ across \$RSET_1\$. This is a fairly "compact" way (in the sense that it is active, not saturated, but requiring fairly low control voltages) to get the current source. – jonk Jan 07 '18 at 17:55
  • I didn't quite understood last two comments of yours but if I understood a part of it, you are trying to achieve constant Vbe with Q6? And Q7 is a constant current source - but why is it biased via the Q6? To compensate something there? Otherwise there would be a simple voltage divider for biasing the base of Q7, right? – Keno Jan 07 '18 at 19:49
  • @Keno Added something at the end to provide some modest explanation of \$Q_6\$. – jonk Jan 07 '18 at 21:37
  • Hmm... All thogether makes sense now. But I am still curious why is the base of Q7 biased via this configuration of Q5 and Q6? And not just a simple voltage divider for its base? Is his base biased that way to monitor current changes or sth alike? – Keno Jan 08 '18 at 11:04
  • And probably my last question to this post, how to determine approx. resistance of overall collector load of Q8, since there is a VBE multiplier and CCS between its collector and positive rail? In my opinion, VBE multiplier could be assumed as low resistance load since it is conducting some current and same for CCS but the collector load would be mainly determined by the emitter resistor of CCS, that is Q7? – Keno Jan 08 '18 at 12:30
  • The Rc resistance see by the Q8 collector at low frequency is mainly determined by the output stage current gain and the load resistance and the output resistance of CCS (Q7) https://electronics.stackexchange.com/questions/333007/power-amp-av-with-current-source/333059#333059 – G36 Jan 08 '18 at 16:41
  • @G36 Output resistance of CCS? You mean "ro" from small-signal model of transistor, which also refers to Early Voltage? In which case value determination of "ro" is impractical, since Early Voltage is given rarely by data sheets. – Keno Jan 08 '18 at 17:47
  • Yes, "ro". But Q7 output resistance is larger than this due to emitter degeneration (negative feedback). And as a rough approximation, we sometimes use this equation r_ce =ro*(re+RE)/re but the rce cannot be larger than ro*beta. And ro = (Vce + Vearly)/Ic – G36 Jan 08 '18 at 18:10
  • @G36 But Early Voltage is impractical parameter because it can be only measured for each individual transistor and is not given by data sheets. How do you deal with it? Do you always measure it (indirectly of course) when you need it in calculus like this one? – Keno Jan 08 '18 at 20:13
  • 1
    @Keno I'm leaving this discussion between you and G36, for now. I didn't worry about the Early Effect much in what I did. I also didn't do a lot of 2nd order effect thinking on the circuit. Your protoboard makes most of this not worth the effort, anyway. So I just did a "once over" and set it free. Don't fret the Early Effect that much, right now. There are some really BAD BJTs for this: the D45H11 (PNP) comes to mind. But by and large you can avoid the worry for now. Worry about it later when you care more about making improvements, not when getting things in a ballpark of working. NFB helps. – jonk Jan 08 '18 at 22:57
  • @jonk Okay, you are probably right. I am asking you for one more thing, could you comment on this question I posted earlier? ...why is the base of Q7 biased via this configuration of Q5 and Q6? And not just a simple voltage divider for its base? Is his base biased that way to monitor current changes or sth alike? – Keno Jan 09 '18 at 05:22
  • @Keno Not at all. Q7 is another current source. As I mentioned, there is approximately two VBEs maintained across Q6/Q5 to reach the base of Q5. This is, in effect, a relatively stable voltage reference. Q7 is an emitter follower, which after losing its VBE, leaves about one VBE across RSET2. So this means about 1 mA of collector current for Q7. I probably should make it more than that as Q10 and Q11 may need 1/3rd to 1/2 of that and I really should have made that perhaps 4 mA or so. – jonk Jan 09 '18 at 09:55
  • @Keno I'm going to fix that problem in the circuit, in case others refer to it for some reason. (Boosting the Q7 collector current.) Note that I'm changing both RSET1 and RSET2. – jonk Jan 09 '18 at 20:55
  • @jonk But why should the curent throu Q7 be increased? – Keno Jan 10 '18 at 07:02
  • @jonk And in general, how should the current of VA and first stage of OPS be compared? I usually use 1:1 ratio - 1 mA throu VA and 1 mA throu Q10 and Q11. This should probably be important since it also effects on loading of OPS and simultaneously considering the decrease of voltage gain, right? – Keno Jan 10 '18 at 07:11
  • @jonk The decrease of voltage gain should be as low as possible and to achieve this, the quiescent output current should be higher.... I think. – Keno Jan 10 '18 at 07:17
  • @Keno The output stage has, at best, a guaranteed current gain of about 9000. At worst, probably half that. This means the base currents for the output stage are about \$400\:\mu\text{A}\$, roughly. I should have at least 5 times that (or 10) for the current in Q7. I'd set it too low before. Better now. By "VA" I think you mean Q8. If so, it has to sink ALL of the unused current from Q7. – jonk Jan 10 '18 at 09:41
  • @jonk But how can you know, whether you need a collector current though Q7 10 times larger then base currents for Q10 and Q11? What would be different (beside larger voltage gain) if collector current of Q7 or Q8 would be 1 mA instead of 4 mA? What stops me from choosing random values for collector current of the VA and input stage? – Keno Jan 10 '18 at 15:41
  • 1
    @Keno In theory, let's say that Q10 and Q11 might need 1 mA, at most. (To simplify things.) And let's say that we set up Q7 to source 1 mA. Then, during peak output times all of the Q7 collector current would be "used up" before it gets to Q8. So Q8 would suddenly have nothing to do. But also, if it was Q10 sucking it up, then there would be nothing to "power" the VBE multiplier, either. This makes designing a predictable VBE multiplier and predicting the "average" load for Q8 impossible. Sure, you must accept variation. But you want to minimize that to some "reasonable" degree. 4 mA helps. – jonk Jan 10 '18 at 16:29
  • @jonk I don't want to bother you but could you just take a peek at this question right here https://electronics.stackexchange.com/questions/351139/understanding-of-dominant-pole-compensation?noredirect=1#comment838147_351139 and maybe add something to it. Because it seems that you are good at everything! – Keno Jan 20 '18 at 19:57
  • @Keno I am not good at everything! Your question treads into math and developing an understanding requires significant exploration of the math. I could provide a circuit example that ***might*** help a little -- it is simple. But I suspect it may lead to more questions than answers. Do you have LTspice installed? You might look at MT-033 from Analog devices and see what you make of it. (It's a tutorial of sorts.) It kind of relates, I think. Your question there, including comments I read, is more a world of questions! And by the way, GOOD ONES!! I'm impressed. I just don't know what to say. – jonk Jan 20 '18 at 23:28
  • @jonk **ANY** contribution you can give to it would most probably enhance my understanding of it! Circuit example wouldn't be bad, would it? At least I could see how this kind of compensation is implemented in practice (if that is what you meant). – Keno Jan 21 '18 at 11:46
  • @Keno Then consider the following [schematic](http://i.stack.imgur.com/yeN9e.png). – jonk Jan 21 '18 at 18:30
  • @Keno I wanted to point out a relatively simple and common approach to making a regulated power supply using a MOSFET and an opamp, which in practice actually will not work right without the added change. It's a simple circuit that illustrates a problem (oscillation) ... and a solution (an integrating capacitance.) A problem is that I'd need more time than I have right now to work you (and also me) through all the details so that it "sticks." (Also, look up *pole zero compensation* while you are on it.) – jonk Jan 21 '18 at 23:23
  • @Keno The goal for something like this is to minimize the number of poles while maintaining one dominant pole, so that the phase shift near the *gain-cross-over frequency* is small. You can get LTspice to generate a Bode Plot for you on these two different circuits I gave you. This is done with a .AC record and where you set those (+) voltage sources to "AC 1" as the value. Run it and plot from 100 Hz to 100 MHz. Then click on each of the two outputs. You will see what I'm talking about, I think. – jonk Jan 21 '18 at 23:38
  • @jonk I get what you meant to explain with these two circuits. And I have already "cleared my mind" with the questions that bothered me/ were unclear. I just made an answer to my own question, summarizing everything G36 and others wrote - do you think you have time to quickly check it out and maybe then add a thing or two to it (now that I understand this topic more in details) ? – Keno Jan 22 '18 at 18:18