Preventing Verilog module from being optimised away

Question

I have tried to put lots of inverters to stress test my Spartan 6 power supply as recommended here. Here is the basic module:

module inverter(
  input wire clk
);
  reg [7:0] inverted;
  always @(posedge clk) begin
    inverted <= ~inverted;
  end
endmodule

I was told that because this module only has inputs, it will be optimised away, and indeed ISE is telling me:

 WARNING:HDLCompiler:1499 - Empty module <inverter> remains a black box.

How can I prevent ISE from optimising away my inverters?

Tie it to an unused output pin? I really dont know, just an idea if I was just wanting to run a test. — Kortuk, Jun 27 '12 at 14:04
You'll probably have to do two things...add Xilinx specific keywords to your code and use compiler switches. I believe that 'KEEP' is the keyword, but check the ISE manuals. Secondly, you'll have to change ISE to let it know not to optimize out unused logic. Optimization is preformed at both at the module and global level, so you'll probably have to add switches for both. — Joel B, Jun 27 '12 at 15:04

score 2 · Accepted Answer · answered Jun 27 '12 at 15:49

You can chain your inverters into a huge shift register, then e.g. tie its ultimate output to a pin. This should do the job while being vendor independent. You shouldn't have to instantiate every module manually, it can be done in a compact way using a generate statement, which I believe even XST understands (although I haven't tried it). See e.g. this forum thread for an example.

Preventing Verilog module from being optimised away

1 Answers1