How is this crystal layout?

Question

After 3 days reviewing my PCB layout before going to production, I'm not really sure about it. It would be great if somebody could give me any advice/comments about this crystal unit layout.

DETAILS: MCU: Atmega328P-AU CLOCK SPEED: 16MHZ

CRYSTAL TYPE: SMD-5032_2P (HERE)

LOAD CAPS: 2 x 22pF

GROUND PLANES: Both 1st and 2nd layer

Sorry if there's something bad in the layout, I'm just 16.

Schematic:

@DanielGiesbrecht: You mean these vias?

This layout looks fine to me. Also, there isn't really that much to screw up on a 16 MHz crystal and a micro. Unless you do weird things like place the crystal 5 cm away. But you didn't so this should work fine. — Bimpelrekkie, Dec 17 '17 at 21:31
Crystal and cap layout looks good enough. Maybe increase the pour clearance a bit for manufacturability. But I would have a bypass capacitor much closer to pins 3/5 GND and 4/6 Vcc. — Spehro Pefhany, Dec 17 '17 at 23:15
related: [Earlier thread (from 2010) about crystal layout](https://electronics.stackexchange.com/a/5608/7036) — Nick Alexeev, Dec 18 '17 at 01:27

Daniel · Answer 1 · 2017-12-17T23:08:14.433

1

One thing I might change (others may have different advice) would be to rotate the capacitors both 180 degrees, so that their ground pads are close together. This would require you to move the crystal and caps a bit farther away from your IC to be able to route, but give them the same ground reference to each other. I would also place a ground via near the two pads.

EDIT

Based on your second photo, I notice that your ground stitching is minimal. Think about how traces slice up your ground plane, and how you can use vias and the plane on the opposing side of the board to "stitch" these slices back together. A few example stitching vias are added in light blue in the image below:

Take the area just below your logo; there are many traces running horizontally on the top side of your board, with red plane split above and below. Placing two vias on either side of the traces uses the bottom ground plane to attach the red pieces back together.

I would recommend not following my example exactly, but instead use it to think about how you can connect your two ground planes together as well as possible, ideally everywhere. This involves finding a balance between maximum number of vias (don't turn your board into swiss-cheese), and best possible stitching.

edited Dec 17 '17 at 23:08

answered Dec 17 '17 at 21:32

Daniel

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My opinion: at 16 MHz, what you suggest is really not needed. If this was running at 200 MHz or more, then I might agree that what you suggest might be better. But not at 16 MHz. – Bimpelrekkie Dec 17 '17 at 21:33
I agree with that. I'd say there's no penalty to doing it though, considering what looks like a lot of free space around it. – Daniel Dec 17 '17 at 21:34
Great! so there's nothing to be worried about. – Amin Mansouri Dec 17 '17 at 21:36
Just added a wider screenshot – Amin Mansouri Dec 17 '17 at 21:39
Added an edit above. – Daniel Dec 17 '17 at 21:41
1

That crystal requires a load of 20pF, but your 2x 22pF (which are effectively in series) only gives 11pF. Use 2x 36pF, that gives 18pF, and the extra pin-to-pin capacitance of typically 2 to 3pF will give you the required 20pF load for optimum crystal accuracy. – Steve G Dec 17 '17 at 21:42
Hi Steve, just added a screenshot of the schematic – Amin Mansouri Dec 17 '17 at 21:52
@DanielGiesbrecht you mean adding vias without any net connection, just placing them? – Amin Mansouri Dec 17 '17 at 21:54
@AminMansouri I mean adding vias connected to the GND net, used to make a more seamless connection between the top and bottom GND planes. Even if it doesn't violate your design rule check, the GND planes may not be well connected overall. – Daniel Dec 17 '17 at 21:57
@DanielGiesbrecht I uploaded a screenshot of the vias – Amin Mansouri Dec 17 '17 at 22:21

How is this crystal layout?

1 Answers1