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I am working on an FPGA design in which I also have to integrate several legacy IP cores. I use asynchronous assertion and synchronous de-assertion for the master reset signal in my design.
I observed that some of the IPs I got use synchronous resets while the others use asynchronous resets.

Will this create any issues during design implementation?
Do I have to modify the IPs to use a common reset method or can I just ignore this? (I have some restrictions in modifying some of the IPs)

rvkrysh
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  • You should not use async resets. If you have them in your design, make sure to synchronize them before connecting to a circuit with sync resets expectations. – Paebbels Dec 13 '17 at 23:59
  • I generally use async resets in the design. But I am making sure that the resets to the IPs are going through a reset synchroniser. However, by using two types of reset methodology in the design, will it cause issues in achieving time closure in the FPGA? – rvkrysh Dec 14 '17 at 15:15

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If I have a design with synchronous reset, and you feed it with an async reset signal which may be asserted at any time, it internally goes via a clocked flip-flop. So for the design, it will be just like a synchronous reset. So it has to work.

Mitu Raj
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  • No, you can not connect a async reset to a circuit expecting sync resets!. You need to add a synchronizer circuit in between. You should not use async resets at all ... – Paebbels Dec 13 '17 at 23:58
  • What if the async reset is latched in Flip-flop in FPGAs ? The output of the flip-flop will be a synced reset I guess ?! – Mitu Raj Dec 14 '17 at 07:23
  • https://www.google.co.in/url?sa=t&source=web&rct=j&url=http://www.doe.carleton.ca/~shams/ELEC3500/asynchronous.pdf&ved=2ahUKEwj6nKGCuYnYAhVBsY8KHVyYA3sQFjAGegQIBhAB&usg=AOvVaw1TTf5Y7yFu1_zCTL20Ez6I -- check this . Since it will go through flip-flop in the synchronous reset design, async reset will work just as sync reset. – Mitu Raj Dec 14 '17 at 12:00
  • I think that's what a synchroniser circuit is meant to do, as suggested by @Paebbels. If I am right, it will also reduce the possibility of metastability. – rvkrysh Dec 14 '17 at 16:45
  • In FPGAs, I don't think you have to care about it, cz it would already be there on synchronous designs. Even if you implement a synchronous adder on FPGA, the input we give via switches on an FPGA board is like asynchronous. We can switch it anytime. But internally those inputs are sampled via flip-flop. Anyway, in the very first flip flop, there is always a chance of metastability. Check https://electronics.stackexchange.com/questions/234861/metastability-error-propagation-with-flip-flop – Mitu Raj Dec 14 '17 at 17:38
  • No one flip flop is not enough. You need at least 2 flip-flops. Using unsynchronized switches in a synchronous adder design is just wrong. There are error in your result, but these errors are to fast for your slow display and you human eye. But anyhow the design is not correct. The point is, if you don't care for correctness in simple design, you will do the same mistakes at 100kHz at 10 MHz and at 10 GHz. If you take a simple PS/2 keyboard bus: If you don't synchronize, you'll get wrong results even in low kHz rates! So do your designs right, just from the beginning. – Paebbels Dec 14 '17 at 21:17
  • In designs with async reset, the issue is in the de-assertion part. When synthesising, FPGA synthesisers automatically add that synchronizer logic for de-assertion part, meeting recovery time and all, to avoid meta stability. I think we have to worry about these things only in ASICs. – Mitu Raj Dec 15 '17 at 12:35
  • FPGA synthesisers adding reset synchroniser automatically is a new information for me. Do you have any links that I can refer, to understand how this works? – rvkrysh Dec 19 '17 at 17:03
  • You can refer to Xilinx Synthesis Guide. – Mitu Raj Dec 19 '17 at 18:17