i want to use example design of GTP transceiver for my ARTIX 7, everything is fine but in the constraint xdc file, i could not find the TX and RX constraint, this is my constraint file, i want to know what is the set_property LOC GTPE2_Channel_X0Y4 is this constraint for TX and RX???do i have to right somthing like Set_property LOC E12 [get_ports RX_P_IN] for RXP???or this constraint is ok?
create_clock -period 8.333 [get_ports Q0_CLK1_GTREFCLK_PAD_P_IN]
create_clock -name drpclk_in_i -period 10.0 [get_ports DRP_CLK_IN_P]
set_false_path -to [get_pins -hierarchical -filter {NAME =~
*_txfsmresetdone_r*/CLR}]
set_false_path -to [get_pins -hierarchical -filter {NAME =~
*_txfsmresetdone_r*/D}]
set_false_path -to [get_pins -hierarchical -filter {NAME =~
*reset_on_error_in_r*/D}]
set_property LOC E10 [get_ports Q0_CLK1_GTREFCLK_PAD_N_IN ]
set_property LOC F10 [get_ports Q0_CLK1_GTREFCLK_PAD_P_IN ]
set_property LOC C25 [get_ports DRP_CLK_IN_P]
set_property LOC B25 [get_ports DRP_CLK_IN_N]
set_property LOC GTPE2_CHANNEL_X0Y4 [get_cells gtwizard_0_support_i/gtwizard_0_init_i/inst/gtwizard_0_i/gt0_gtwizard_0_i/gtpe2_i]
set_property LOC GTPE2_CHANNEL_X0Y5 [get_cells gtwizard_0_support_i/gtwizard_0_init_i/inst/gtwizard_0_i/gt1_gtwizard_0_i/gtpe2_i]
set_property LOC GTPE2_CHANNEL_X0Y6 [get_cells gtwizard_0_support_i/gtwizard_0_init_i/inst/gtwizard_0_i/gt2_gtwizard_0_i/gtpe2_i]
set_property LOC GTPE2_CHANNEL_X0Y7 [get_cells gtwizard_0_support_i/gtwizard_0_init_i/inst/gtwizard_0_i/gt3_gtwizard_0_i/gtpe2_i]
connect_debug_port dbg_hub/clk [get_pins -hier -filter {name=~*DRP_CLK_BUFG*O}]