Improved Differential Amplifier

Question

I made this circuit as shown below:

schematic

^{simulate this circuit – Schematic created using CircuitLab}

After those improvements with current mirror and constant current source were considered, this is what I got.

The emitter currents through both of Q3 and Q4 were calculated to be 1mA, but when measured approx. 900uA each. Voltages were split equally between each of sub-stage of amplifier - voltage across current mirror = 10V, voltage across differential transistor pair = 10V and voltage across constant current source = 10V (measurements actually showed up a bit different results - Vmirr = 0.8V, Vdiff = 19.2V, Vccs = 10V).

As seen measured values aren't really as expected.

Why is there only 0.8V across the current mirror (Vmirr + Vre1)? Why are both Q1 and Q2 in saturation?

"*After **those** improvements*", from what to what? Maybe you're talking about an earlier question? (Do you expect everyone to click your profile picture => look at questions => find which question you are talking about?) — Harry Svensson, Nov 02 '17 at 16:32
Did you check whether all the devices are in the active region? — sarthak, Nov 02 '17 at 16:34
Why do you think that the voltage should split equally (10V)? For sure this is not the case. The voltage at Q4 collector will be around Vcc - Vbe2 - Ic4*Re1 = 30V - 1.6V = 28.4V — G36, Nov 02 '17 at 16:50
@sarthak differential stage is in active region, so is the constant current, but current mirror is in saturation and I don't know why. — Keno, Nov 02 '17 at 16:53
From KVL. Q2 work as a diode connected BJT, hence Vce2 = 0.7V. So the Q4 collector voltage is Vcc - Vbe2 - Ic4*Re1 = 30V - 1.6V = 28.4V — G36, Nov 02 '17 at 16:54
@HarrySvensson No, I don't expect that. But I assumed readers of this question will have some fundamental knowledge about differential amplifiers and know that this circuit is not basic diff. amp. (with only passive resistors). — Keno, Nov 02 '17 at 16:56
@G36 How else would you made a current mirror? Without connecting collector to the base of Q2? — Keno, Nov 02 '17 at 16:57
We can't do it. But in real life, this is not the problem because we are taking the output signal from Q3 collector. https://electronics.stackexchange.com/questions/333502/differential-stage-av-value-with-current-sources/333536#333536 Can you measured the voltage across Re1 and Vce2 — G36, Nov 02 '17 at 17:04
@Keno in that case can you lower the biasing of the differential transistors? — sarthak, Nov 02 '17 at 17:15
And this circuit may behave "strange" because without any external load or negative feedback. The diff gain is huge so small mismatch in the circuit can mess a bit. — G36, Nov 02 '17 at 17:20
@G36 Yup. There needs to be a load in here. Often, something like a VAS. Something current-driven. — jonk, Nov 02 '17 at 17:30
@Keno What did you figure as your current through \$R_{e_2}\$? You do NOT have very stiff biasing there. Discounting the rest of the circuit I get about \$2.3-2.4\:\textrm{mA}\$. — jonk, Nov 02 '17 at 17:31
@keno Put some of your own design values on the schematic. Tell us what you figured, how you figured it, and why you wanted it. What was your goal? And may I assume these are all discrete parts? — jonk, Nov 02 '17 at 17:41
@jonk Actually the current is around 2 mA measured, but calculated should be as you said. About the biasing, I was really only experimenting here so I don't really know if the voltage divider across Q5 is good? Or would be better if I would have constructed voltage divider with three resistors - from Vcc to base of Q4 then from base of Q4 to the base of Q5 and the third resistor would be between the base of Q5 and ground? — Keno, Nov 02 '17 at 17:45
@jonk All parts are discrete, my goal was to achieve the best possible current balance between Q3 and Q4. — Keno, Nov 02 '17 at 17:46
@G36 Voltage across Re1 is bit less that 0.15V, Vce1 is 0.8V but Vce2 is 1.5V. — Keno, Nov 02 '17 at 17:50
@G36 Yes, the output current is taken from Q3 as you said but Q4 is in this case used as negative feedback driver, where currents between Q3 and Q4 should be balanced, if I'm not wrong. — Keno, Nov 02 '17 at 17:52
@Keno You will need a way to make adjustments for differences in \$V_{BE}\$ (\$I_{SAT}\$) and \$\beta\$ between the transistors. Not to mention the need for variations due to the Early Effect. (\$V_{CE}\$ of \$Q_2\$ and \$Q_4\$ can be worked out but how did you choose to work out the \$V_{CE}\$ of \$Q_1\$ and \$Q_3\$, for example?) How do you plan to "adjust" this for balance, in practice? — jonk, Nov 02 '17 at 18:04
@jonk I mean, I could simply put a potentiometer between one of voltage divider (that also passes the base of Q3 or Q4) and then adjust it so both Ie of Q3 and Q4 would be equal. But that is not the point, at least not in the theory. Plus I don't really get it how could the current flow through diff. transistor pair with no bias across the diff. transistor bases but only a constant current source somehow pushing both of transistors to conduct current... — Keno, Nov 02 '17 at 18:46
@jonk ... as commented by Bimpelrekkie in my other question ( https://electronics.stackexchange.com/questions/337467/differential-amplifier-input-line-level-signaling/337468#337468 ). For me that is more important question. — Keno, Nov 02 '17 at 18:47
@Keno I think you need to break down your goals into pieces. For example, your current sink design is ... not so good. You have a current mirror instead of collector resistors -- not so good unless you have a place for the difference current to go -- which you don't. Take a breath, break this project into parts, starting with a part that does not depend on the other parts, and work forward. Understand each piece, one at a time. Would that make sense to you? Or are you suggesting that you understand all of this, but your neck of the universe is weird? — jonk, Nov 02 '17 at 19:07
@Keno I looked at bimpel's comment. Makes sense. You need headroom. What's the question there? — jonk, Nov 02 '17 at 19:11
Let us [continue this discussion in chat](http://chat.stackexchange.com/rooms/68110/discussion-between-keno-and-jonk). — Keno, Nov 02 '17 at 20:23
Install a 1Kohm load on collector of Q1, tied to +20 volts. Then examine the circuit. — analogsystemsrf, Nov 03 '17 at 05:19

score 1 · Accepted Answer · answered Nov 02 '17 at 19:36

Let's start out by looking at your \$Q_5\$ current sink.

You are using a voltage divider using \$R_5\$ and \$R_6\$ to set the base voltage. \$Q_5\$ is being treated as an emitter follower, using \$R_{e_2}\$ to set the collector's sinking current. I just wrote a page on this, here. There, you'll find the following equation:

$$I_{C}=\left[\frac{\beta}{\beta+1}\right]\cdot\left[\frac{V_{TH}-V_{BE}}{R_E}\right]\cdot\left[1-\frac{1}{1+\frac{\left(\beta+1\right)R_E}{R_{TH}}}\right]$$

In your case, \$R_{TH}\approx 44.329\:\textrm{k}\Omega\$ and \$V_{TH}\approx 1.705\:\textrm{V}\$. I can guess from this that you assumed \$V_{BE}=700\:\textrm{mV}\$ so you were expecting about \$1\:\textrm{V}\$ across your resistor, \$R_{e_2}\$, making for a current of \$\approx 2.13\:\textrm{mA}\$. However, the \$3^{rd}\$ factor above says about 65% of that would be more realistic; or about \$1.4\:\textrm{mA}\$. This is because your resistor divider network is not stiff. It's floppy.

So how might you improve it? Well, you could stiffen up the divider. That's the obvious path. Another might be to convert this to a current mirror. Either way, you should provide a means by which you can set the value to a preferred value (or, at the very least, sit down and actually measure what you got.) But being able to make adjustments to get a preferred design value would really be better.

Better still would be to work out a method that is independent of the voltage rail for at least one order of magnitude change. (It can be done with discrete parts!!) But it involves the use of three transistors in an odd arrangement (Wyatt) and only really works at a design current that is perhaps too low for your desire. But it is stable over temperature by taking advantage of the temperature coefficient of metal film resistors and of copper wire itself. (On the order of 3300 ppm per K.) But I think this would be for a different day.

I'd recommend working out a current sink that doesn't move much if you heat it up or cool it down a bit and also stays close to a nominal value if you swap out transistors. Want to start there? Or do you feel that you do not need any help on this point and want to take a different step?

Improved Differential Amplifier

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