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Today I learned about the concept of memory training for DDR2, 3, and 4 (I'm not sure if DDR1 has it). The purpose of memory training is to correct for skew in data, address, and command bits being sent between controller and memory (presumably using a programmable analog delay?).

Also important for DDR is the concept of length matching, to ensure that each bit in a given word in DDR arrives to the DRAM/to the controller within a clock period. This is to ensure the data receiver "sees" the correct bit pattern when it's time to latch.

These seem to be accomplishing the same task. Clearly, I can look at any board with DDR memory and see length-matched traces, but it leaves me wondering: What physical, technical, or business decisions make it impractical for a DDR(2-4) controller itself to compensate for skew due to mismatched lengths, as long as the incoming clock is skewed as well to after what the controller determines is the latest-arriving bit?

cr1901
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Timing skews are not only a function of trace length, but a variety of factors: temperature, voltage, etc. With high frequency systems, even a minor skew can drift your edges into setup and hold violations. Thus the need for runtime, dynamic data eye training.

Sittin Hawk
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length matching in a byte is to align all the bits, however, the training takes care of aligning the byte lanes and depending on the algorithm/technology also the isi by adjusting drive/receive parameters

Alex Novickis
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I start to believe the training can compensate the length mismatch, at least to some an extent. Though just a guess. Laying out a board is costly, so most people will just match the lengths, though just my guess again. I do see a reference board with largely mismatched lengths. Heard of a processor that can compensate lengths by setting internal registers. Though not sure whether those can add to support of my guessed belief.

minghua
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