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I am very comfortable with the usage of the Moore's law and its impact on microelectronics. However I had always associated Moore's law to the gate length scaling as a factor of square root of 2 every two year. (This then leads to a related performance increase which is of our interest)

Only recently I came to realize Moore's law is about number of transistor per area which, I known, was very tightly linked but not anymore (For instance the 14nm technology does not have devices with 14 nm gate length but rather 14nm width finfets).

Still in most official definitions they do not use the term ‘number of transistor per area’ they would rather use the terms:

  • "number of transistor per dense integrated circuit" (Wikipedia)
  • "Number of component per integrated function" (Original graph from the paper 1965)
  • “components per chip” (IEEE, IEDM 1975 paper)

And thus my question:

What is the definition of a ‘dense integrated circuit’ or ‘integrated function’ and how does it relates to Area in Moore’s law?

Jonathan
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A "dense integrated circuit" simply means that the transistors are as small as possible and as close together as possible.

If you designed an integrated circuit where the transistors take more space than strictly needed the it is not "dense" meaning, it could have been made smaller.

What Moore writes relates to designs that are as small as possible. His statements simply do not apply to designs that are not "dense" as such designs do not have maximum functionality for a given chip area.

An "integrated function" is a function implemented on a chip. For example a 32 bit multiplier is a function and needs a certain amount of logic gates meaning it needs a certain size on a chip. By comparing technologies on the function the comparison is fair and not comparing apples against pears.

Comparing more complex designs like a microcontroller quickly becomes unfair as the functionality of different products (realized in different IC manufacturing processes) is seldom identical.

Bimpelrekkie
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  • the number of transistors for a 32bits multiplier is 21000. this would mean that number of component is 21000 fixed on this specific integrated function. How does it comes that we consider as Moore's law the transistor density (per area) instead? – Jonathan Oct 17 '17 at 09:51
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    @Jonathan *How does it comes that we consider as Moore's law the transistor density (per area) instead?* Because the 32 bits multiplier will take 21000 transistors **independent of the process technology you use** (for example 0.18um CMOS or 7 nm CMOS). Moore's Law relates to technology so using something that's not dependent on technology (how much transistors does it take to build a 32 bit multiplier?) isn't relevant. What is relevant is **how small** can we make a 32 bit multiplier and also: how many 32 bit multipliers can we put on one chip? – Bimpelrekkie Jul 30 '20 at 14:29
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What is dense?

Depends on era.

When CMOS started in early 70’s we had SSI (small scale integration( gates), MSI, (counters) LSI, in 80’s VLSI etc. Now lithography can be <1% of those and defect free wafers and chips much larger with 10^10 transistors.

Moore’s Law generalizes the results of product technology advances needed to reduce feature size and chip size to achieve growth in qty / IC with low defects.

Tony Stewart EE75
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  • Then what is the impact of this history on the Moore’s law? Or maybe there was never real definition for this law? – Jonathan Oct 18 '17 at 11:18
  • No matter how hard anyone has tried for commercial success, this has been the practical growth llmit. – Tony Stewart EE75 Oct 19 '17 at 05:39
  • I am sorry but I don't understand the comment... is it maybe just a personal opinion about current issues with scaling vs performances? What I am currently concerned only about is the definition of it. – Jonathan Oct 19 '17 at 07:21
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Moore's Law has been generalized to include a number of different measures. The most common is the doubling time of computing power for a given cost, which is not necessarily directly related to the areal density of transistors.

As one of the answers above mentions, we had SSI, LSI, VLSI and later ULSI (ultra large scale integration) but at some point we ran out of descriptions and nobody bothers with categories like that any more.

Dirk Bruere
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  • The generalisation 'doubling computing power for a given cost' sounds to me like another definition. All These is now leading me to think that there isn't any real law with a definition but then rather a concept which consist of doubling a parameter that lead the integrated circuit to better performances... – Jonathan Oct 18 '17 at 11:21
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    Well, the law was never a Law - just an observation made at the time – Dirk Bruere Oct 18 '17 at 12:46
  • well, I am still hoping that what has driven the whole microelectronics economy for more than half a century is a bit more than 'just an observation made at the time' – Jonathan Oct 18 '17 at 13:23
  • Moore’s Law is nothing more than trend analysis, with time – Tony Stewart EE75 Oct 19 '17 at 05:29
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    @TonyStewart.EEsince'75 It's become a bit more than that. It is a kind of PR target for almost all semi manufacturers. A self fulfilling prophecy – Dirk Bruere Oct 19 '17 at 08:17
  • The cost of R&D and implementation of billion dollar foundries with higher resolution and lower defect rates with larger wafers and higher yields per chip to advance the trend may be viewed from many perspectives but the cost and technology barriers limit the growth to what it has been. – Tony Stewart EE75 Oct 20 '17 at 01:36
  • @TonyStewart.EEsince'75 Which implies that one the resolution limits of Moore's Law are reached at around the 1nm level the prices of chips will drop as that's the end of the line for fab equipment R&D, which no longer has to be amortized over a 3 year cycle – Dirk Bruere Oct 20 '17 at 07:57
  • Yes so chips may become larger with greater yields using more cores where 256 is theoretically possible if heat can be displaced. – Tony Stewart EE75 Oct 21 '17 at 22:48
  • @TonyStewart.EEsince'75 Eventually I expect some kind of printing/moulding process to replace existing lithography, and we will finally make a successful jump to wafer scale integration – Dirk Bruere Oct 22 '17 at 11:26