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I am currently working on a PCB with DDR2 on it. We are bringing out the DDR2 CLK, DQS signals using pogo pins to make some timing measurements. The length of the pins are about 5 cm. The problem is that every time the pogo pins make contact with the test points (of clk and DQS), we see noise on both DQS and CLK. I removed the pogo pins and started experimenting by adding small stubs on the test pads of clock. What I noticed was that by adding stubs of longer length > 1.2cm on Clock, I could introduce noise on DQS and the level on noise is somewhat propotional to length of the stub. Is this because the signals reflect from the stub and cross couple to DQS? I tried the same thing on vias instead of test pads and it is more prevalent. Can some please throw some light on why this happens and how it can be avoided?

Sdatt
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  • In RF designs we used stubs to change a track's impedance. In that case it was used for making filters or to (not sure of the proper English words) tune impedance. If the impedances of a previous step and a next step are not properly matched, you get reflections in the signal line (noise/distorsion). I'm in the impression that this is what happens here too. Approx. what frequency are you working at? – jippie Jun 04 '12 at 07:00
  • Thanks for the reply jippie. The clock runs at 400MHz. I did some more experiments and now see some ground noise everytime I add the stub. The rise time increases with addition of the stub. Obviously, ground noise is feeding back in to DQS. Question is why would adding a pin or a stub on clock line cause ground bounce so badly. – Sdatt Jun 04 '12 at 07:24

1 Answers1

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The Short Story

This is caused by reflections. The DQS and CLK signals travel down the un-terminated line and, finding an improperly-matched impedance to completely absorb the signals, a portion of the signal will "bounce" back from where it originated. The reflected signals (the ones that bounce back) will be summed with the signals currently being generated which is evidenced as "noise" on your desired signal.

The Slightly Longer Story

Signals that change (especially those at higher frequencies such as that of DDR) are much more influenced by what is in the signal path than static (DC) signals. Signals become more difficult to deal with because everything in the signal path (vias, parallel traces, stub traces, etc) can have some form of resistance, capacitance, or inductance to it which can affect the signal adversely. This is known as complex impedance. Your stub-trace actually looks like some form of complex-impedance in parallel with your DDR, thus changing the signal properties and (from what you're saying) causing reflections. By changing the length of the stub you are essentially changing what the parallel termination looks like and causing it to either absorb more of the signal or reflect more of the signal depending on how well the impedance of the stub matches the impedance of the IC generating the signals.

Joel B
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  • Yup, that is about the clarification I had in mind. Has been way too long ago for me to explain it in proper words. +1 – jippie Jun 04 '12 at 17:58
  • Thanks Joel B and jippie. I agree, I changed the resistance of the stub and observed how the signal reflections change. My best option would be to use the shortest possible pogo pin with very low capacitance and inductance. – Sdatt Jun 05 '12 at 03:01
  • Shorter could be better. It really depends on how well "matched" the impedance is to the frequency of operation. Another option is to use resistors to allow you to connect the debug pogo signals when needed and you can de-populate them for your end product. That way you don't have stubs hanging around possibly interfering with your performance when they're not needed. – Joel B Jun 05 '12 at 15:19