1

I was experimenting with a simple voltage level shifter to convert a signal from 5v to 3.3v.

Then i went to simulate my circuit in orcad pspice, and i need help understanding what is causing the voltage spikes. I'm using a pulse generator to pulse a 1kHz signal in to the gate.

Is it the rise and fall times of the pulses that is causing the spikes? enter image description here

enter image description here

MatBE
  • 60
  • 1
  • 10

2 Answers2

1

The spikes are caused by the input signal edges leaking into the output through the MOSFET's gate-to-drain capacitance.

You can add a gate resistor, or a BJT which would be cheaper (don't forget the base resistor).

Another solution for 5V to 3V3 conversion is to use 74LVC logic gates which take a 3V supply but accept 5V on their inputs.

bobflux
  • 70,433
  • 3
  • 83
  • 203
  • Thanks for your answer! Adding a resistor in series with the gate seems to remove the negative spike completely, but not the positive spike. What can i do to reduce that? The negative spike comes when the input signal of the gate switches to 5v. so it makes sense that the resistor reduces that one. But what about when the signal goes from 5v to 0v? – MatBE Sep 29 '17 at 09:16
  • Why is the spike a problem? – bobflux Sep 29 '17 at 09:29
  • It's not necessarily a problem, i'm just wondering what is causing it. – MatBE Sep 29 '17 at 09:32
  • I need the level shifting for a digital signal. Converting a 5v (logic 1) signal from the uart transmitter of my microprocessor, to a 3.3v (logic 1) signal. Will the Uart transmitter be able to drive the mosfet gate? and do you reckon that the voltage spike would be a problem for the 3.3v receiver? – MatBE Sep 29 '17 at 09:35
  • 1
    In a simulator not everything is modeled, not all series resistances and parasitic capacitances are present. As a result of that you get more "sharp" signals in a simulator resulting in overshoot spikes like you see. In the real world these spikes will not be present or at least much smaller. So you can safely ignore them. I do the same even for much more complex designs with hundreds of transistors. If you would include all parasitic components (including inductance of PCB wires) you would see much smaller or no sharp spikes. But for a UART level shifter, that's 5 bridges too far ;-) – Bimpelrekkie Sep 29 '17 at 09:39
  • Don't worry, the receiver won't care... just make sure the pullup is low enough to in value to have a rise time that suits your serial baud rate. – bobflux Sep 29 '17 at 09:47
0

i need help understanding what is causing the voltage spikes.

Spikes happens due to parasitic elements present on every device. Even a simple resistor has it in real world. You are lucky for your simulation model have it, so that you can predic how it will behave with assembled physical components.

You can reduce it by using a RCD snubber, but the drawback is the addition of a delay on the transistor's off transition and decreasing slew rate as well.

aluis.rcastro
  • 136
  • 7