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What's the difference between the following two circuits? Note that the capacitors are DC blocking, and the FET is on.

circuit diagrams with (a) load connected to ground and (b) load connected to -Vdd

I understand that usually, the load is connected to ground. But what would happen if it was connected to the negative DC bias? What about the positive DC bias? Does the mode (constant-mobility, constant-velocity, ...) make a difference? I saw this circuit in a small-signal analysis problem.

Of course, if the capacitors are NOT high enough that they become an open circuit at DC and a short circuit in AC, then that will affect the circuit in obvious ways. I'm asking about any other effect this would have.

Null
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Andres Riofrio
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2 Answers2

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The two circuits are equivalent except:

  1. The voltage accross the capacitor. In this case it looks like the capacitor needs to be able to handle Vdd volts either way but with different polarity. If you know something particular about the bias point and the amplitude of the signals, then you might possibly be able to get a away with a lower voltage capacitor in one of the cases.

  2. Where the load current flows. The Vdd current requirement could be different between the cases.

  3. The effect of noise on Vdd. Case B is more susceptible to this than case A.

In both cases the signal accross Rl is the same, assuming no significant noise on Vdd.

Olin Lathrop
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  • My guess would be that Rd can be larger in case B at the same drain current and therefore output impedance will be higher. – jippie May 29 '12 at 19:36
  • @jippie: No, that doesn't make sense. The capacitor blocks DC, so Rl has nothing to do with the DC bias point. Since it's AC coupled, it doesn't matter what DC offset Rl is at, only the impedance of what it is connected to. The impedance of ground is 0, and we are making the assumption that Vdd is a good supply and it is close to 0 too. The two cases are then indistinguishable from the FET's point of view. – Olin Lathrop May 29 '12 at 20:03
  • I mean the output impedance of the transistor // Rd. That is the output impedance Rl 'sees'. Sort of Thevenin thing. – jippie May 29 '12 at 20:13
  • @jippie: But Rd will be identical in both cases, the output impedance of the transistor//Rd will be the same, and Rl will present the same load. Impedance-wise the two circuits are identical because both ground and Vdd have 0 impedance. – Olin Lathrop May 29 '12 at 22:48
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When you connect the load to the ground then its works normal n it only depends on the FET working mode whether it is conducting or not n voltage drop across the load will be V(Load voltage) but

When connected to the negative bias then the difference of the voltages of Vss and Vdd is appeared at the load.(neglecting drain-source voltage).

If you need more clarification Your welcome...!!!!!!!!!!

Gouse Shaik
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