0

I just found this site and read a few great interesting articles but nothing that would solve my problem I am hunting since a while.

I have a OpAmp circuit with a N-FET source follower that regulates the current of some LED's. LED current is set at 700mA. The ripple on the LED voltage source is at around 590kHz and is seen at 20mV on the source shunt of 0.3R. This feedback goes directly to the OP-. The OP+ has a quite stable reference voltage. This means I can measure a 20mVpp ripple between OP+ and OP-! When I measure the OP output and OP- I see that both signals have the same phase and are NOT inverted. This means that 20mVpp on the 0.3R shunt generates 40mV on the gate of the FET with the same phase. But it should be the opposite. So I guess the OP is not stable at this frequency. Otherwise it works fine and regulates the current accurate and quick. It's just that there is lots of ripple noise (and thus current ripple) and I would like to get rid of it! What am I not seeing or did wrong here? Any hints would be appreciated!

LedDriver

Here a scope picture. The reference voltage at OP+ is stable. But I can measure a 20mVpp ripple between OP+ and OP-! This means the OpAmp is not really doing what it should do.

On the picture is the gate voltage with the shunt voltage as comparison. The shunt voltage (OP-) is yellow with about 20mVpp ripple. The pink is the gate voltage at around 1.75V and it has the same ripple but with the same phase and 40mVpp. I always measured with the short, spring type GND connectors on the probes and took the OpAmp GND as reference.

OP- vs. Gate voltage

So my question is here: why doesn't the OpAmp try to remove the ripple as the feedback of the source is directly connected to OP-? Why is it running at the same phase? The GBW is at 2.2MHz. Isn't this circuit running at unity gain? What am I missing? Thank you very much for any hints/inputs!!!

6o4o
  • 3
  • 3
  • 1
    Are you maybe picking up noise from a switching power supply somewhere? Have you tried with very short leads on your scope probe (using a spring probe instead of the ground lead on your scope probe?) – JRE Jun 30 '17 at 11:22
  • 1
    Possible duplicate of [Stability problem in unity-gain opAmp](https://electronics.stackexchange.com/questions/69506/stability-problem-in-unity-gain-opamp) – brhans Jun 30 '17 at 11:25
  • 1
    ... And https://electronics.stackexchange.com/questions/313170/op-amp-output-not-stabilizing-in-precision-current-sink – brhans Jun 30 '17 at 11:26
  • You have an unused op amp in your circuit. If this is left floating as shown, it will likely cause oscillations. – Glenn W9IQ Jun 30 '17 at 11:32
  • Open OpAmp is used, i just removed the components to make it clearer... – 6o4o Jun 30 '17 at 13:46
  • brhans - thnx for the links! The first one i read throughly a few days ago but was a different problem/setup. But the second link is interesting, thnx – 6o4o Jun 30 '17 at 13:51

2 Answers2

2

You have oscillations because there is a chance that the circuit is unstable due to the gate-source capacitance of the MOSFET adding significant phase shift within the negative feedback closed loop containing the op-amp.

Simple analysis would make you think that because the MOSFET is connected as a source follower (regarding negative feedback) any gate capacitance will be neutralized but this isn't the case if you look into the detail. The gate source capacitance is about 1nF and approximately one-third of this will be "seen" by the circuit because MOSFETs are not perfect voltage followers. Your waveform shows this: -

enter image description here

Source voltage (yellow) is about 2/3 of gate voltage (pink) implying that between gate and source is a voltage of about one-third hence residual capacitance projected back to the op-amp output via the 100 ohm resistor is also about one-third. It should be noted that I have assumed the capacitance to be about 300 pF but, on further inspection of the DS it would be more like 450 pF.

So you have a 100 ohm resistor and approximately 300 pF (or maybe 450 pF) forming an extra phase shift. This will add 45 degrees phase shift at about 5 MHz. However, it doesn't mean that the circuit won't oscillate at lower frequencies - the phase shift will be less than 45 degrees of course but, if there is enough added phase shift to bring the phase margin down to zero at above unity gain, you get an oscillator.

Clues lie in this picture taken from the op-amp data sheet: -

enter image description here

It's not absolutely clear cut because TI (in their infinite wisdom) have not delivered a graph of pure open loop gain and phase so this is the nearest we can use. For the gain, anything above the red line is potentially able to oscillate. For the phase anything equal to the blue line will cause oscillations providing gain is above the red line.

As you can see, when 100 pF is placed on the output, the op-amp avoids turning into an oscillator i.e. phase margin becomes zero at about 3 MHz but gain has just dropped to about 7 dB below unity = no oscillation.

What is the loading effect of the 100 ohm resistor and residual gate capacitance (~300 pF)? Difficult to be precise but if it's like adding a 100 pF capacitor then it's a fair comparison BUT, remember the 100 ohm and ~300 pF add probably +30 degrees of phase shift around the loop at about 3 MHz so it'll oscillate, possibly about 1.5 MHz for a guesstimate.

The ripple on the LED voltage source is at around 590kHz and is seen at 20mV on the source shunt of 0.3R

This is significantly below the 1.5 MHz that I estimate but the mechanism outlined above cannot be ruled out given the lack of proper information in the data sheet. At 3.3 volts the phase margin may be worse for instance. My estimate for residual gate capacitance might be significantly low as well. Poor grounding may also contribute.

Remember also that the LEDs are fed from an independant supply (9.5 volts) that may have significant ripple at 560 kHz and this will not be greatly reduced by the op-amp because it only has a gain overhead of about 15 dB i.e. it won't cope well with this as a disturbance.

Andy aka
  • 434,556
  • 28
  • 351
  • 777
  • Nice way of explaining things +1 .When I was at UNI I specialised in repeating control systems . – Autistic Jun 30 '17 at 12:39
  • Great, thank you very much Andy! I had the feeling about the gate cap and the other links brhans posted where you also answered on that topic but I could not explain myself on how exactly it works. Now i understand it better! Now i will try the 2nd link (of brhans) where a cap is put from output to Op- as feedback. – 6o4o Jun 30 '17 at 13:53
  • @6o4o the other answer was a slightly different scenario - the output was truly at the emitter (or source) and the load would not be so low that gate-source capacitance would be a big problem and generate significant residual capacitance. Your feedback resistor is only 0.3 ohms and below an ohm you really need to look at the phase shift. As a fix, you could try lowering the 100 ohm resistor and, if it isn't that, maybe it's noise coming from the 9.5 volt rail. – Andy aka Jun 30 '17 at 13:59
  • I lowered the 100R to 0R, changed nothing. Yeah, the 580KHz comes from the 9.5V , it's a DcDC! But i expected the OpAmp to fight the noise and keep the current constant with no ripple. The OpAmp voltage (3.3V) is from an LDO and it had no noise at all. – 6o4o Jun 30 '17 at 14:56
  • @6o4o - my last paragraph in my answer says effectively the following - when the open loop gain is low, you cannot expect an op-amp to cope as it would when the open-loop gain is high (lower frequencies or DC). At 580 kHz, the open loop gain looks like 15 dB and this is pitifully small to expect an op-amp to regulate out the modulating current from the 9.5 volt rail. It's all down to the equations for errors in op-amps. – Andy aka Jun 30 '17 at 17:25
  • So in other words either i get an Opamp with better gain margin that will cope with the cap. load or i get a FET with a lower capacity. The FET is anyway to big for the 1A i will pull max... i thought maybe i can get away with a capacity feedback from output to minus input but i guess that won't solve the fact that the OpAmp has a low gain margin... – 6o4o Jul 01 '17 at 05:58
  • An op-amp with higher gain-bandwidth-product is what you are looking for to cope with the wobble from the 9.5 volt rail. Or you try and smooth that rail better before feeding it into the LEDs. Regards the FET, if you only need 1 amp then maybe use a bipolar transistor - there's no issue with capacitance there - it'll be 100 times lower. – Andy aka Jul 01 '17 at 08:53
  • Hello Andy. I will check with another OpAmp and see how it works out. – 6o4o Jul 01 '17 at 10:06
  • I still wonder: the DS diagram you posted, the phase shift margin is lower with a cap load compared to the same diagram with no cap load (but same RL). Is the phase shift of the capacity load not already included in this diagram or do you have to add the phaseshift the capacitor load makes additional to the diagram phase shift at a specific cap. load? Example: let's assume like above the 100pF generates +30° phase shift. On the diagram at 100pF I get 30° margin at 1.6MHz. On the gain I read at this f 2-4dB gain. Can I calculate like that? This would mean it will oscillate at 1.6MHz right? – 6o4o Jul 01 '17 at 10:16
  • The loading effect on the phase margin is as shown but the RC phase shift is indeed another addition. It is marginal that is why I considered other mechanisms in my answer. I get 1.5 MHz as a potential hot spot but, even if it doesn't oscillate it will ring when transients come along. – Andy aka Jul 01 '17 at 10:24
  • You could of course, using your simulator open the loop and do an AC analysis. Inject into the gate and see what gain and phase come from the opamp output then use various loads to make the phase margin head towards zero. Like I said in my answer, TI don't give the best info for calculating this sort of thing precisely. – Andy aka Jul 01 '17 at 10:28
  • Hello Andy I changed the 100R to 1k and also 10k. I realized, that the 20mV ripple doesn't bother me on the LED supply (9.5V). The OpAmp is to adjust the FET power loss (reduce drop voltage) and is quite slow when doing that. I just don't want the FET/OpAmp to ring and also it doesn't really need to get rid of the power supply ripple at the end. With the 1k I get an RC 353kHz with 450pF. This should filter out the ripple frequency, so that the OpAmp doesn't start to oscillate above that frequency. I might even go higher with the resistor just to be safe. – 6o4o Jul 03 '17 at 09:03
  • Making R bigger can help - the time constant increases and although the op-amp does have higher o/l gain at the lower frequency, the phase margin is bigger too. As frequency increases, there is more gain reduction due to the RC and this helps also. Usually this works. A cleaner method turns the op-amp into an integrator by adding a resistor between FET source and IN- and putting a local capacitor between OUT and IN-. Alternatively, if you made the 100 ohm a s/c you can see that you will never get 0 deg with a gain greater than unity. Or, use a BJT. – Andy aka Jul 03 '17 at 09:17
  • I tried 10kR and the output still oscillates a little bit at 100kHz. I will try the integrator route! I got the Analog Devices article with some infos. We got only 1-2mm space on the PCB and this OpAmp is really small and I would like to avoid to search for another one. Thanks again Andy!!! – 6o4o Jul 03 '17 at 11:11
  • @6o4o if you are happy with this answer please consider formally accepting it. – Andy aka Jul 03 '17 at 11:18
0

Operating close-to-rail, the Rout becomes higher and higher.

Assume 1Kohm Rout (TI gives no data nor curves, just how drive strength collapses near the rails) at VDD/2, and 10Kohm if "close to rails".

With 1MHz UGBW and 10Kohm, the equivalent inductance is (1uH and 1MHz is j6.3 ohm) 1,600uH.

Fring of 1,600uH and 300pf (Andy aka Cin number) is sqrt[25,330/(Luh*Cpf)] in MHz. Fring(MHz) is sqrt(25,330/1,600*300) or sqrt(25,550/500,000) or sqrt(1/20) or 0.2MHz

What is your Fring?

analogsystemsrf
  • 33,703
  • 2
  • 18
  • 46