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My understanding is that there will be setup time violation. As setup time is defined as minimum time the data input must the stable before applying clock. But what will be the output if we violate setup time?

new_ecl
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    If you *violate* a spec of like *anything*, generally the behavior would be undefined. Or, if the manufacturer have defined it for some reason (for example for safety reasons), it will be a *bad* one anyway. – Eugene Sh. Jun 22 '17 at 14:50
  • Note that in some cases (FPGAs in particular) the flip-flops are designed with "negative hold time" specs. In these flip-flops it's not a violation for the input to change at the same instant as the clock edge. – The Photon Jun 22 '17 at 15:38
  • Related question discussing the typical behavior when you violate setup or hold time: [If a flip flop has a setup violation and goes metastable, is it guaranteed to settle to the input value when it finishes oscillating?](https://electronics.stackexchange.com/questions/26981/) – The Photon Jun 22 '17 at 15:44

2 Answers2

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Data changing too late prior to the clock edge is a setup time violation. Data changing too soon after the clock edge is a hold time violation. You are proposing to change the data simultaneously with the clock edge, so it is unclear which without looking at the innards of the flip-flop. In any case the result is undefined.

Neil_UK
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Entrepreneur
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    Some flops have negative setup time or negative hold time, and on such a flop the behavior would be defined in the presence of a simultaneous clock and data event. – supercat Jun 22 '17 at 15:34
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You need to examine the data sheet to see what it says.

Most discrete D flip-flops have positive setup and hold times, which means a simultaneous transition of both clock and D will violate both. In this case, you can say nothing definite about the output. It may go high, it may go low, it may become metastable, in which case there is no guarantee that it will settle to high or low in any finite time. In practice, for any given flip-flop, it's likely to settle in the same state each time.

Some D flip-flops, especially those in the I/O of FPGAs, may have a negative setup time, or a negative hold time, in which case the behaviour is defined by the data sheet, and you can rely on it to always do that.

Neil_UK
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