Simulation pass but Emulation fails

Question

I have learnt that sometimes fpga code may work correctly in simulation, but will fail when emulate.

But I couldn't find any example scenario where simulation pass but emulation fails. Anybody who knows that kind of scenarios, please help..

Thank You!!

ps:
I meant behavioral test as simulation and post-route test as emulation.

What do you mean under "emulation"? I guess "simulation" means running your RTL in a software simulator, what is your "emulation" then? And which "simulation" do you mean, behavioral? post-translation? or final back-annotated after all placement and routing? — Ale..chenski, Jun 19 '17 at 16:20
@AliChen I meant `behavioral` test as simulation and `post-route` test as emulation. — Ramesh-X, Jun 19 '17 at 16:48
Using emulation can be rather difficult sometimes because of hardware compatibility and checksums that the code throws out to make sure the hardware is valid for what you're doing. — , Jun 19 '17 at 22:07
By post-route test, do you mean running the timing model produced by your synthesis tool (Xilinx ISE, Quartus etc.) under a testbench in a simulator (ModelSim etc.) ? Which software tools are you using for each of these steps? — TonyM, Jun 20 '17 at 04:04
@TonyM: I'm using a testbench file I wrote and `ModelSim` in `Xilinx ISE`. — Ramesh-X, Jun 20 '17 at 08:20

score 1 · Answer 1 · answered Jun 20 '17 at 11:00

What you're doing isn't emulation - please don't use that term for it, you'll confuse people.

This is all simulation, first of the behavioural VHDL straight from your text editor, then of the timed model in VHDL produced by ISE during synthesis. The timed model will be full of VHDL that includes delay statements and delays terms to simulate the time delays of the final circuit.

Emulation is using a circuit that's different to the final intended circuit but behaves similarly enough to be useful in test or development. That's hardare and something quite different. Your ModelSim simulation does not get through 100 ms of its virtual time in 100 ms. It's a simulation.

Regarding your question on your pre-synthesis behavioural VHDL and post-synthesis VHDL timed model...

In your behavioural VHDL, you can write and simulate many things that can't be turned into a logic circuit. You can also write things that can be turned into a logic circuit but not a useful or good one. Many people write 'wish list' VHDL that does what they want in the pure language environment of the simulator, then find that it cannot be turned into a useful circuit or the circuit they want. Designing digital logic in VHDL means to envisage a practical digital circuit, sometimes quite broadly, and then to write VHDL that implement that circuit.

For example, during synthesis the synthesis software tool will strip out anything that does not result in an output because not circuitry is required to implement it. For example:

  entity NOWT is
    port(
      RST : in  std_logic;
      CLK : in  std_logic
      RES : out std_logic
    );
  end entity NOWT;

architecture RTL of NOWT is
  signal t : std_logic;
begin

  Toggle : process(RST, CLK) is
  begin
    if (RST = '1') then
      t  <=  '0';

    elsif rising_edge(CLK) then
      t  <=  not t;

    end if;
  end process Toggle;

end architecture RTL;

In simulation under a testbench exercising RST and CLK, signal 't' can be seen to invert on every CLK rising edge after a suitable RST.

The programming file and VHDL timed model from synthesis will contain no circuitry. No outputs are driven.

What to look for when fault-finding behavioural VHDL that does not produce the correct circuit is a subject in itself. I have seen some terrible ones, such as:

  if rising_edge(START) then
    a  <=  1;
  elsif rising_edge(STOP) then
    a  <=  2;
  elsif falling_edge(ABORT) then
    a  <=  3;
  end if;

The only edge-triggered logic element that an FPGA/CPLD has is a register, with a single edge-triggered clock input. So if this is synthesised, the synthesis tool will attempt to make this circuit out of LUTs i.e. out of AND, OR, XOR and NOT gates. It will also give you warnings about it because its bad design. This is just writing a 'wish list' of functions rather than considering what digital logic circuit can do the job required.

score 0 · Answer 2 · answered Jun 19 '17 at 17:24

If your RTL doesn't include explicit timing delays for non-blocking register assignments accounting for causality of clock-data relationship, something like

stateB <= #0.1 stateA;

then the post-route simulation (and actual test) most definitely will fail.

Simulation pass but Emulation fails

2 Answers2