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JFET:

I am trying to calculate the upper cut-off frequency of this circuit. Gain gave me 5, as it did in the teacher's solutions. But I'm applying the expression to the condensers and it's giving me negative values! The initial circuit is as follows (the generator is ideal): enter image description here

\$c_{gs}=8\,pF;\,c_{gd}=4\,pF;\,I_{DSS}=7\,mA;\,V_P=-4\,V;\,r_0\rightarrow \infty\$

The small signal model I did with the calculation that is giving me a negative value is as follows: enter image description here

The teacher's solutions are as follows (I did not understand where the final solution expressions come from): enter image description here

New model: enter image description here

First try: enter image description here

Null
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Carmen González
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1 Answers1

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Your equivalent model is wrong. Cgd should go to ground and so should Cgs.

The Miller effect is only apparent in common source operation where the input is at the gate and the output is at the drain. The effective input capacitance will have Cgd multiplied by the voltage gain of the circuit (+1).

Cgs is directly in parallel with the input signal so does not affect the frequency response.

In this circuit the upper cutoff frequency is just determined by Rd and Cgd (goes to ground) as a simple first order RC. Ro is infinite so it can be ignored.

The output of he JFET can be considered a constant current source. Rd and Cgd are in parallel.

This can also be re-arranged to be a voltage source feeding a capacitor through a resistor. (A current source across a resistor is equivalent to a voltage source feeding through a resistor).

Kevin White
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  • I do not understand how I have to draw Cgd. Can you make a model drawing for small signs, please? A friend of mine told me that there was no Miller effect for the common gate. Is there Miller's effect for the common Drain? – Carmen González Jun 05 '17 at 02:35
  • He said that to calculate the upper cut-off frequency would have to replace each parasitic capacitor, by a voltage source and calculate the Thevenin equivalent. After calculating the upper cut frequencies, the total upper cut-off frequency of the circuit is given by the lower frequency between Cgd and Cgs. I tried to do this but did not get to the teacher's result (18 MHz). – Carmen González Jun 05 '17 at 02:37
  • You should notice that the teacher's solution only has Cgd and Rd in the equation. In your equivalent model just ground the upper left node. All except the Rd and Cgd then drops out. – Kevin White Jun 05 '17 at 02:44
  • I did not realize your last comment. Anyway, I did not realize how the teacher came to expression. He just put the final result, which is not trivial for me (or anyone in my class ...). I made a new equivalent model in post. Can you see if it's correct, please? – Carmen González Jun 05 '17 at 02:48
  • If the equivalent model is well designed, what is the next step to find the upper cutoff frequency? What do I have to do? – Carmen González Jun 05 '17 at 02:51
  • Your equivalent circuit is correct. Cgs is across the input that is a voltage source so it will not affect the frequency response. Ro is infinite so you can delete it from the equivalent circuit. The only frequency dependent part of the circuit is Rd and Cgd. – Kevin White Jun 05 '17 at 03:01
  • And what do I do with Rd and Cgd? What calculations do I have to make? – Carmen González Jun 05 '17 at 03:16
  • I'm sure you have learnt how to determine the cutoff frequency of a single resistor and capacitor. Use that knowledge. – Kevin White Jun 05 '17 at 03:19
  • I tried to calculate the cutoff frequency considering only Cgd. In the post,(I put the calculations in the post, please take a look), but it's giving me 71 MHz and the teacher gives 18 MHz. What am I doing wrong? – Carmen González Jun 05 '17 at 08:57
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    In common gate amplifier the miller effect do not occur. And additional you have Rin = 0Ω So, we will have only one pole Fc ≈ 0.16/(Rd*Cgd) ≈ 0.16/(2.2kΩ*4pF) ≈ 18.2MHz – G36 Jun 05 '17 at 14:56