I was reading the LPDDR2 spec today out of curiosity. While browsing the spec I became curious about "how might one hypothetically design a minimal working LPDDR2 PHY on paper/for simulation, perhaps to release as an open source design?"
According to this answer, the internals of how LPDDR2 works are confidential. Additionally, according to this article, most SoC designers today use a (LP)DDR PHY IP. So schematics of memory chips and PHY internals are unlikely to be found online. However, I imagine there are people browsing EE.SE who would know about designing PHYs, and that some design techniques are not specific to (LP)DDR PHYs apply anyway.
Does there exist literature on how a memory PHY of might be designed at the schematic level (including simulation and DRC), or general techniques on how to design a (LP)DDR PHY?
If no to the above question, I'll reduce the scope to my immediate questions about LPDDR2, using the spec as a reference.
LPDDR2 specifics that all logic level I/O is relative to a V_ref (page 160), and that the memory controller generate voltages relative to V_ref to indicate high or low, even if V_ref is out of spec. What is the rationale (analog behavior) behind this design decision? How would a PHY generate these voltages (a simple summing amplifier?)?
LPDDR2 requires that supply voltages always obey certain requirements (page 26), such as voltage rails always being no more than 100mV within each other. What analog behavior within a LPDDR memory would require this behavior, even during the power-up phase, when voltages are likely to be erratic? Would circuitry inside the controller or memory chip be able to enforce these requirements?
Can the voltage-level generation/regulation circuitry as described in the above two bullet points be analyzed/created using pencil and paper approximations, or are the analog effects required to meet the conditions too precise to be reasonably analyzed on paper (thus, requiring a simulator)?
