Op amp circuit calculations

Question

A question on stack exchange exists regarding the following circuit:

Brief: The original question concerns finding component values to amplify a signal ~10 times. I would like to know how the man who answerred (Olin Lathrop) arrived at certain values.

Question One: How is the output impedance derived?

With R1 and R2 10 kΩ, the output impedance of the divider is 5 kΩ.

Question Two: Formula for C2?

R1 and R2 only need to be equal to make 1/2 the supply voltage. You mention no special requirement, like battery operation where minimizing current is of high importance. Given that, I'd make R1 and R2 10 kΩ each, although there is large leeway here. If this were battery operated, I'd probably make them 100 kΩ each and not feel bad about it. With R1 and R2 10 kΩ, the output impedance of the divider is 5 kΩ. You don't really want any relevant signal on the output of that divider, so let's start by seeing what capacitance is needed to filter down to 20 Hz. That is 40 µF, which is rather large. OK, lets make R1 and R2 higher, like 100 kΩ each. Now C2 only needs to be 4 µF to filter down to 20 Hz. I'd make it 10 µF because that will be readily available, and extra filtering here does little harm.

The following does not agree with the 40 microfarad outcome $$\frac{1}{2\pi \cdot R \cdot f}=\frac{1}{2\pi \cdot 5\times 10^3 \cdot 20}$$

Question Three: What can be done to reduce the stabilisation time?

Note one issue with this topology. Frequency-wise, C3 is acting with R5, but the DC level that C3 will eventually stabilize at is filtered by R4+R5 and C3. That is a filter at 1.4 Hz, which means this circuit will take a few seconds to stabilize after power is applied.

Thanks in advance

Daniel

Answer 1

How is the output impedance derived?

For the purpose of the output impedance of a resistor divider, the two resistors are in parallel. 10 kΩ // 10 kΩ = 5 kΩ.

The following does not agree with the 40 microfarad outcome

You are right. I must have punched a wrong button on my calculator and not noticed at the time. I have edited the answer you linked to.

What can be done to reduce the stabilisation time?

With the existing topology, stabilization time is related to gain. You can reduce the gain, possibly splitting that gain stage into two stages with lower gain. Or, use a different topology altogether.

Chosing the right topology to best meet the requirements is a important part of designing circuits.