Delta count overflow

Question

I'm making JKnRnS master slave flip-flop, here is my code:

library IEEE;
use IEEE.std_logic_1164.all;

entity JKnRnS is
  port(
       C : in STD_LOGIC;
       J : in STD_LOGIC;
       K : in STD_LOGIC;
       nR : in STD_LOGIC;
       nS : in STD_LOGIC;
       Q : inout STD_LOGIC;
       nQ : inout STD_LOGIC
  );
end entity;

architecture JKnRnS of JKnRnS is                                                            

signal Q_int: std_logic := '1';
signal NQ_int: std_logic := '0';

signal a,b,c1,d,f,e,notC: STD_LOGIC;
begin    
a<=not(C and J and nS and NQ_int);                                 

c1<=not(d and a and nS);

d <= not(nR and b and c1);

b <= not(Q_int and nR and K and C);

e <= not(notC and c1);

f <= not(d and notC);

Q_int <= not(NQ_int and e and nS);

NQ_int <= not(nR and f and Q_int);

notC <= not(C);

Q<=Q_int;
nQ<=NQ_int; 

end architecture;

which works fine, but when I change it into:

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_MISC.all;

entity nand_3 is                                
    generic (t_rise: TIME:= 0 ns; t_fall : TIME:= 0 ns);
     port(
         in1 : in STD_LOGIC;
         in2 : in STD_LOGIC;
         in3 : in STD_LOGIC;
         out1: out STD_LOGIC
         );
end entity; 

architecture nand_3 of nand_3 is 
begin   
    process (in1, in2, in3) is
    begin
    out1 <= not(in1 and in2 and in3);  
    end process;
end architecture;


library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity nand_4 is
     port(
         in1 : in STD_LOGIC;
         in2 : in STD_LOGIC;
         in3 : in STD_LOGIC;
         in4 : in STD_LOGIC;
         out1 : out STD_LOGIC
         );
end entity;                                               

architecture nand_4 of nand_4 is
begin
     process (in1, in2, in3, in4) is
     begin
         out1<=not(in1 and in2 and in3 and in4);
     end process;
end architecture;

library IEEE;
use IEEE.std_logic_1164.all;

entity JKnRnS is
  port(
       C : in STD_LOGIC;
       J : in STD_LOGIC;
       K : in STD_LOGIC;
       nR : in STD_LOGIC;
       nS : in STD_LOGIC;
       Q : inout STD_LOGIC;
       nQ : inout STD_LOGIC
  );
end entity;

architecture JKnRnS of JKnRnS is                                                            

signal Q_int: std_logic := '1';
signal NQ_int: std_logic := '0';

signal a,b,c1,d,f,e,notC: STD_LOGIC;
begin    

E1: entity work.nand_4(nand_4)
    port map(in1=>C, in2=>J, in3=>nS, in4=>NQ_int, out1=>a);
E2: entity work.nand_3(nand_3)
    port map(in1=>d, in2=>a, in3=>nS, out1=>c1);

d <= not(nR and b and c1);

b <= not(Q_int and nR and K and C);

e <= not(notC and c1);

f <= not(d and notC);

Q_int <= not(NQ_int and e and nS);

NQ_int <= not(nR and f and Q_int);

notC <= not(C);

Q<=Q_int;
nQ<=NQ_int; 

end architecture;

I get an error: KERNEL: Error: KERNEL_0160 Delta count overflow. Increase the iteration limit using -i argument for asim or the matching entry in simulation preferences. What is wrong here?

Have you tried a non-zero delay in nand_3? – scorpdaddy May 01 '17 at 20:03 — scorpdaddy, May 01 '17 at 20:03

score 0 · Answer 1 · answered May 01 '17 at 19:59

A delta is the internal 'virtual time' step of the simulator, the propagation delay of every virtual gate. During simulation, an assignment to signal 's' leads to a delta delay before the simulator goes around updating every signal dependent upon 's'. After another delta, it does the same again for any signals dependent upon those ones and keeps going until no more signals are dependent upon the last ones updated.

So if, for example, you have two concurrent assignments that create a feedback loop:

a <= b; b <= a;

then the simulator gets stuck in a loop: updating a means b needs updating means a needs updating etc. To stop this, the simulator has a limit on the number of deltas of dependent logic it will process before it stops. In practical terms, this is the number of levels of logic gates feeding each other that it will support. By default, this is set to 5000.

If you have more than 5000 logic gates in a chain, you have to change the simulator default but, let's face it, you've got bigger problems anyway with your circuit...

In practice, ModelSim doesn't behave that gracefully with a continuous loop. I've occasionally written endless loops in testbenches by forgetting to put a 'wait' statements in a process. ModelSim doesn't stop after so many deltas, it just locks up. (Hope it's been fixed in newer versions.)

So you need to examine your design here and look for assignments that create a continuous feedback loop without a wait statement in their path.

I've eyeballed through the OP code and isn't this the problem then: Q_int <= not(NQ_int and e and nS); NQ_int <= not(nR and f and Q_int); — Migol, May 01 '17 at 20:06
Yes, or one of them - well spotted @Migol. Easy test would be to put an 'after 10 ns' at the end of the assignment and see if the problem goes away. This puts a 'wait' delay into a concurrent statement. You should see oscillator behaviour on the Wave windows if this is one of the problem statements. — TonyM, May 01 '17 at 20:44

Delta count overflow

1 Answers1