Think about the problem that is being solved for a second. You want the inside of the chip to run at some frequency, you want to be able to choose different frequencies for various reasons (or pick a specific one for one or more reasons). You take a crystal (accurate) based oscillator and you want to multiply that essentially.
Think of the things your professors said not to do, dont do this or the circuit will oscillate. The term metastability might have come up in the lecture as well. In this case you actually want that, a semi-controllable unstable oscillator that you can loosely control.
So you need to have a loosely controlled oscillator, something you can build in silicon, wrap that with a control system (PLL) and there you go. Say I want to turn 4Mhz into 16, so lets say I want my VCO then to be 16x that. I take the output of the vco put it into a counter, I sample/reset the counter every tick of the 4MHz clock, if it is less than 16 counts then I adjust the VCO to go faster, when it gets to 16, great, so I keep that control setting, if it drifts to 17 I slow it a little, drops to 15 I speed it a little...a control system...I design the oscillator and its control such that it cant go out of control to fast, dont want one 4Mhz cycle to be 16 counts then the next 47 then the next 3. Thus the time it takes to settle a PLL based clock in a processor/chip before you can use it (usually documented in the datasheet). Then I can use another (digital) counter to divide that 16x down by for so I went 4*16/4 = 16mhz.
Doesnt have to be a digital counter, just one possible way to do it, it can be some sort of analog solution (thus the term PLL, phase locked, using the phase difference), but at the end of the day it needs to track N times the reference clock which was the whole point. The delta used in the control system doesnt have to be a whole count off, that would possibly be pretty bad, you could have a digital count that is a coarse grained control loop and then for the fine control loop you use an analog comparison of the reference clock state change and the Nth VCO state change.
Your PLL output is not going to be as good as the reference clock, it is going to have jitter to it, that is expected it uses a control system, so this is implied.
You may or may not be old enough to know what 7400 logic is. But you could take an inverter and feed it back or take an odd number of them and see what happens. It makes no sense on paper if the output is a 1 then input is a 1 then the output is a 0 then the input is a 0, assuming an instantaneous state change. Electricity is bound by the "speed of light" through a material...it has a speed limit...that limit creates a delay, so if you can kick the circuit off into oscillation it will hopefully continue to oscillate. Search for ring oscillator on wikipedia.
A quote from wikipedia
"The voltage-controlled oscillator in most phase-locked loops is built from a ring oscillator"
You can certainly make a NOT gate in silicon on a chip, what other circuits can you make, and what in those circuits can you control in silicon. You cannot make a resistor with a wiper, you are not going to wrap wires around a core and make an inductor (although as with a pcb you can horizontally wiggle a trace back and forth), but you cannot vary that trace once it is placed on the chip, nor make the plates of a capacitor move, nor move a wiper along a metal to make a mechanical variable resistor. Sure you can absolutely make and use a varicap. As pointed out at wikipedia they are commonly used in VCOs.
Vericap on wikipedia also leads into frequency multiplication, where you create a harmonic the filter it out. But would that then need a phase locked loop?
Can you make a circuit, you can build on a chip, that is a voltage controlled oscillator, wrap a PLL around it to somewhat control it to either exactly multiply the reference clock by N or to multiply it by X then divide by Y to get the desired result (not uncommon for the VCO frequency to be in a range higher than the PLL output frequency to be divided to the desired frequency). Yes, obviously it has been done countless times. Problem is there is more than one solution, we cant give you a single answer here if that is what you are after, if there are 100 solutions and someone posts one, they are 99% wrong...
You want to know how they do it in a computer processor? Depends on the processor, the foundry, the process used, the IP used, and which pll in that processor, there may be several, and they might have used a different one for each, depends on the application (core cpu, ethernet/network, pcie, video, etc), the answer can vary at the same foundry with the same chip company but with a different process, each process may dictate or grant the opportunity for a different solution, or not...look at sandy bridge and ivy bridge, not sure exactly how much of it was the same it is intel after all, but it was declared a die shrink from 32nm to 22nm, how much IP was the same from one process to the other, the high level microcoded archtecture, sure just verilog re-compile, but the specific gates, and IP like the I/O pads and PLLs and such, were those complete replacements? Possible.
So IMO your question is not a fit for this site, it does not have one answer, it cannot be summed up in detail with a single circuit, so are you after the concept of how it works, that is sorta okay as a question as that sorta has an answer, see wikipedia or see above. Or are you specifically wanting the circuit for a specific chip from a specific foundry with a specific process using specific IP? Your question is too broad...If you change it to ask a question with one answer, then perhaps someone here can give a single accurate answer.
Spending only a handful/dozen hours reading is not enough to understand the concept with some example circuit details, it can take years in college to get the foundation required, that is more than a couple dozen hours of reading wikipedia. The answers are already there, but the understanding of what is being said might take years of study. Is that the problem here, is that your question?
You said you read all the related articles so: you saw the vericap comment you saw the ring buffer and that comment about VCOs, you read up on PLLs and control systems in general, you examined what a NOT gate was with example circuits. So what specifically do you not understand, what specifically is your question? Something that has an answer.
