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I would like to ask for advice.

Europractice supports many fabs and technologies for custom asic design (fab list). Lib support list of those technologies are public (for example UMC 130 nm LL). I checked all of public lists, and nowhere found dram support.

I am looking for opportunity to design a dram device (for example on 130 nm if that is possible). Which fab i should sign for?

cocox
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    Like I told you in another question, DRAM requires a special process. Only a few factories make DRAM. I doubt that there are any MPW possibilities on a DRAM process. Almost all MPWs are CMOS based and you cannot make proper DRAM in CMOS. – Bimpelrekkie Mar 28 '17 at 20:38
  • @FakeMoustache: It would certainly not be possible to make DRAM with anything near the density of a mass-market DRAM without using processes optimized for that. On the other hand, I would think that a three-cell dynamic memory design might be more compact than a static design. The storage element would be the gate of a MOSFET #1 whose source is grounded. That gate would be connected to a "write" bus through MOSFET #2 and, and the drain of MOSFET #1 is connected to a read bus through MOSFET #3. – supercat Mar 28 '17 at 22:40
  • @FakeMoustache I got it. I want dram, that requires spec technology, what no one else would use, so no design cost advantage for me by mpw based offers. Even if i lost that advantage, Europractice offers a way to get insight into front end design steps for easy, and that is the advantage i would go for. Problem is, i cannot recognize, what i need. Is there any fab / technology on Europractice's list i should look for? – cocox Mar 28 '17 at 22:53
  • @supercat do you mean something like design on start of that document ( http://ece.ut.ac.ir/classpages/F84/AdvancedVLSI/Lecture%20Notes/chapter12-2.pdf ) "3-Transistor DRAM Cell"? – cocox Mar 28 '17 at 23:01
  • @cocox: That's exactly what I was thinking of. Nowhere near the density of one-transistor DRAM cells, but if one needs to get a large amount of memory on the same die as everything else and can afford the power consumption and access limitations it would seem like such a design should achieve pretty good density. I'm not sure what the maximum refresh time would be, or how big the banks could be, but I would expect that a layout which used groups of 16 rows could achieve a good space savings compared to a static design, and would probably be reliable if rows were refreshed every few us. – supercat Mar 28 '17 at 23:05
  • Possible duplicate of [Can multi-project wafer service merge projects with different number of layers?](http://electronics.stackexchange.com/questions/293853/can-multi-project-wafer-service-merge-projects-with-different-number-of-layers) – winny Mar 29 '17 at 05:17
  • @winny i dont know what do you mean. Marked question was about a concepction opportunity for an answer of simple yes or no, even if threads there wandered a bit away, because of question was not simple to answer. This one question is about which fabs nda to sign to start front end design of a project. I dont know why you flagged this question to that. There is no logical connection between the two. – cocox Mar 29 '17 at 09:09

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DRAM processes are usually just mean that you have a trench capacitor with a high density pattern option. I know for a fact that those GF processes in your list have a trench capacitor, and I'm confident that the other 40nm or smaller nodes will as well. I use DRAM instead of SRAM when I need more than about 6MiB because the charge-amps required for SRAM end up using more power than the DRAM refresh.

As an example, this answer has an illustration of my work from a 14nm SOI process where I get about 8-bits DRAM per the area of a single FLASH gate (non-FLASH process), which is about the same area as the cost of 2-bits of SRAM.

Here's the kicker, you will need the NDAs to see what is actually in the design kits. For example, the GF 24nm white paper only lists a fraction of the devices that I see in the kit.

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b degnan
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  • (Sry for previously deleted posts here.) I would like to ask for even more advice. I downloaded NDA request form for GlobalFoundries from EuroPractice website, and form demands me to choose technology, i want access for. There are technologies with exact name in range of 22nm .. 55nm (for example "22FDX", "28SLP", "55LPx-NVM") and "Other" option. I not found exact technology names on GF website, neither i know how to ask them about what EP will recognize. I would use 110 or 130 nm to design a dram, and looking for exact technology name for that. Where can i find exact technology name(s) ? – cocox Mar 29 '17 at 15:41
  • @cocox Well, it'll be an option on the process. The suffix usually just shows whether it is a high speed, low power, analog, etc process. You should just ask for the 130nm (the feature size is much smaller than that) and see what options you have. Also, I don't know if 130nm has trench caps, but I've not been on that process in ages. – b degnan Mar 29 '17 at 16:07