Sample & Hold circuit not working for negative half cycle

Question

I have made a Sample & Hold circuit using Multisim but after simulating oscilloscope showing sampled version of input waveform for positive half cycles only. I have used MOSFET as a switch with controlled voltage and its working fine.

My question is why I am not getting sampling of negative half cycle even though MOSFET is open circuited?

Try to think this: what is the mosfet Vgs during the negative cycle? Also, search "transmission gate" — Vladimir Cravero, Mar 15 '17 at 16:18
You should also consider that your BS170 MOSFET includes an intrinsic diode. — user2233709, Mar 15 '17 at 16:29

score 1 · Answer 1 · answered Nov 17 '18 at 14:48

By connecting the body/substrate to the source, your negative cycles are biasing the intrinsic diode that conducts in reverse discharging your capacitor. You need to connect the substrate to the lowest voltage in your circuit.

It is also worth noting that, in the negative cycle, your Drain and Source terminals become swapped. This is not an issue for this application.

However there remains a problem, the maximum voltage on your capacitor will be determined by the Vto of your FET. This leads to higher and higher impedances as the voltage rises.

To avoid this, a complementary PFET is placed in parallel with the NFET. This arrangement is known as a pass-gate.

score 0 · Answer 2 · answered Mar 16 '17 at 14:02

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your drive to Mosfet is only positive voltages via V1. If V1 was tied to -12v instead of ground, and driven 0 to 20v, would work better. But as Vladimir said, you still need to get over Vgs.

answered Mar 16 '17 at 14:02

Mikel

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Sample & Hold circuit not working for negative half cycle

2 Answers2