VHDL vs SystemC library

Question

Today I learned about SystemC, a C++ library that make development on FPGA easier. (for people that know C++) Apparently, it is as efficient as VHDL (speaking of performance) and faster to learn and code.

Will VHDL disappear since they have the same performance with lower development time? What is the pros and cons of using one instead of the other?

Possible duplicate of [SystemC vs HDLs](http://electronics.stackexchange.com/questions/156075/systemc-vs-hdls) — Voltage Spike, Mar 08 '17 at 20:16

score 1 · Accepted Answer · answered Mar 08 '17 at 20:16

1

No, VHDL is like assembly, you get exactly what you ask for and you are designing on a lower level. System C is like a higher level language, and in the end it gets translated to VHDL or Verilog anyways, but you aren't always going to get the lower level optimizations. System C is better if you have a lot of the same things to do, like build image filters with a lot of multiplications and adds. Which would be a real pain to implement in VHDL.

answered Mar 08 '17 at 20:16

Voltage Spike

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SystemC can also be designed at the same level as VHDL. But yes, the analogy is quite accurate as SystemC is usually converted to VHDL/Verilog for synthesis – Shashank V M Jul 20 '20 at 09:27

VHDL vs SystemC library

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