Using only NAND and NOT gates to represent a logic function that isn't an SOP/POS?

Question

I understand that I should repreatedly use deMorgan's theorem until I am left only with NAND/NOT gates. This is easy when the starting function is an SOP/POS. However when it isn't, I get confused as to what my steps should be (both agebraically and graphically). Consider the function below:

whose circuit looks like this:

I think I can do it algebraically but apparently it is possible to do it graphically (which should be the simpler approach). I can't get my head around doing it graphically, as the process is a little more involved than it is with SOP/POS. Can anyone give me a hand?

Answer 1

That expression has ANDs, ORs(+), and NOTs('). You already have the NOT. A NAND followed by NOT is AND. A NAND preceeded by NOT for each input is OR.

Answer 2

So graphically, replace each gate with it's NAND equivalent.

For an OR gate:

^{simulate this circuit – Schematic created using CircuitLab}

Remove double NOT gates (if they occur). NAND2 and NAND3 can be removed in the following schematic.

^{simulate this circuit}

Edit...

First part of circuit:

^{simulate this circuit}

In this circuit, NAND3 & NAND4 and NAND7 & NAND8 are redundant and can be removed.

^{simulate this circuit}