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When connecting several AXI4-Lite slaves, must I use some kind of interconnect? If it is guaranteed that each slave decodes a distinct set of addresses, is it possible that the slaves would set their data outputs to high-z and be connected together?

haggai_e
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  • Actually there is such interconnect, it is created by Vivado itself –  Feb 07 '17 at 11:46
  • Can you add a link please? If I'm using Vivado, how should I make Vivado add it? – haggai_e Feb 07 '17 at 11:48
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    Create project->create block design->add zynq->add AXI slave->run connection automation (blue link on top of block design) –  Feb 07 '17 at 11:56
  • @GregoryKornblum, can I use the interconnect IP with plain verilog files? (without creating a block design?) – haggai_e Mar 14 '17 at 09:14
  • I have no idea. I think, by this time you are more experienced than me :D –  Mar 14 '17 at 15:34

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Looks like there are implementations of AXI4-Lite slaves that always provide a valid output even when the address is not in their range. This makes such a bus configuration impossible. I guess using a crossbar is a must.

haggai_e
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