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For example, this is the gate charge curve of a p-MOSFET:

curve

Let's say this p-Mosfet works as a simple high-side switch for a load. This load will have significantly more resistance than the mosfet in it's ON-State, so the voltage across the MOSFET will be very small.

I assume the ID is the current that will flow in ON state and that VDS is the voltage in OFF state here, is that correct?

Also, how would this curve change if the Id was very low, 1mA? (For example, we're switching a 24V supply for a 24k Ohm load, the voltage drop across this particular p-mosfet would be in the vicinity of 5mV in that case.

In other words, I need to know how the total gate charge to switch the MOSFET will change if I'm switching a load with much more resistance than the R_DS_ON.

JMC
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  • This curve defines the Gate charge current during transition, approx current is Ig=Q/Vgs*dVgs/dt = CdV/dt and is not affected by load on drain. Steady state the Gate current is near 0. – Tony Stewart EE75 Jan 08 '17 at 21:41
  • Also Ciss rises rapidly for Vds <5V towards 0V by >75% – Tony Stewart EE75 Jan 08 '17 at 21:48
  • If the load on drain does not effect it, why is a specific drain-current given in the upper left corner of the graph? I am not referring to gate current anywhere in my question. – JMC Jan 08 '17 at 21:48
  • The curve you show only applies to gate Q vs Vgs thus only implies Ig(t). The specs show Q near max Id current for 2 different Vds in linear mode (not switched to low Vds) – Tony Stewart EE75 Jan 08 '17 at 22:04
  • I know that that is what it shows, but I don't understand to which time frame the VDS figure in the image refers. Is it the voltage between drain and source when the FET is in OFF state or when it is in ON-State (before or after the switch-on?) – JMC Jan 08 '17 at 22:10
  • See figure 13 in your datasheet – Tony Stewart EE75 Jan 08 '17 at 22:28
  • Figure 13 is a circuit that labels the voltage source as VDS, which would lead me to believe it is the off-state voltage, however, main question still stands. What is the significance of the ID drain-current figure and how does a lower ID (because of a higher load) affect the total input charge? – JMC Jan 08 '17 at 22:34
  • The curve applies to both states. One end applies to ON, the other end to OFF, and the rest of it applies to switching between them. (And it would be very similar at other drain currents, that number is probably the test condition). –  Jan 08 '17 at 22:35
  • I know the *curve* applies to both states, but the VDS figure can only refer to one, as the VDS drops when the channel is open. – JMC Jan 08 '17 at 22:45
  • does this response not help?http://electronics.stackexchange.com/questions/66660/why-is-the-gate-charge-curve-miller-plateau-of-mosfets-dependent-on-vds?rq=1 – glen_geek Jan 08 '17 at 23:03
  • It implies that it's the what I referred to as "VDS in the off-state". But it doesn't talk about the effect of the drain current. http://imgur.com/gzcIyGh In this nmos's datasheet they tested fixed Vds and varied Id. How would this look if I had Id=~1mA? – JMC Jan 09 '17 at 00:06
  • @JMC since you have the advantage of the datasheet but unable to interpret it, why not share the link, so we can help. It ought to be clear. – Tony Stewart EE75 Jan 09 '17 at 01:13
  • http://www.mouser.com/ds/2/149/2N7002-8405.pdf this is the datasheet of the second image, but my problem isn't about any specific mosfet. I just need to know if it will rise extremely with very low Id or if if will still be in the general vicinity. – JMC Jan 09 '17 at 01:17

2 Answers2

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how would this curve change if the Id was very low, 1mA? (For example, we're switching a 24V supply for a 24k Ohm load... how the total gate charge to switch the MOSFET will change if I'm switching a load with much more resistance than the R_DS_ON.

The Gate charge graphs supplied in most datasheets don't cover this scenario, so I decided to do my own tests. The answer is:- probably not much.

I tested a BS107 on a 12V supply with various loads ranging from 0.1mA to 100mA, driving the Gate with 10uA constant current to measure the accumulated charge.

At all load currents the time for the Gate to reach +5V was 84us, showing that the same amount of charge was accumulated. However there was a noticeable change in the 'plateau' voltage that occurs due to Miller effect as the Drain voltage goes down, which ranged from 1.8V at 0.1mA to 3V at 100mA.

Here is the scope trace for 1mA load current, showing Gate voltage plateauing just below 2V. At lower and higher currents the waveform was the same except for the plateau being at different voltages.

enter image description here

While the Gate voltage is plateauing the FET is operating in its linear region dissipating high power, so when switching high current you need to get through it quickly. However at low current the plateau voltage is lower and dissipation is less of a concern, so you might be able to get away with weaker and/or lower voltage Gate drive.

Bruce Abbott
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  • Interesting test. – Rev Jan 09 '17 at 08:04
  • Thanks you for testing it! I assumed that on a very low load current the miller plateau would begin only very shortly above Vth which your test seems to confirm, and my fear was that because of the longer transition the miller plateau might become absurdly long, but apparently that is not the case. – JMC Jan 09 '17 at 12:51
  • Could you show the testing circuit as well? – emnha Sep 09 '20 at 06:42
  • It's been so long I don't remember the exact circuit. I _think_ I used a PNP transistor as a 'constant current' generator like [this](https://electronics.stackexchange.com/questions/446097/square-wave-to-sawtooth-wave-using-two-bjt) possibly triggered with a 555 timer. – Bruce Abbott Sep 09 '20 at 07:54
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The importance of the gate charge data to the designer is illustrated in the Vgs vs Qg .

This is a FET pulse V,Q charge curve to choose I, t tradeoffs.

  • e.g. The current required to switch gate charge Qg=15nC with Ig=1.5A, while device Vds is drained from 80V with a max of 12A then the transition time is 10 nS. It follows that if 15 mA is supplied to the gate, then switching occurs in 1 us.

  • This is based on gate charge is the product of the gate input current and the switching time. These simple calculations immediately tell the designer the trade-offs between the amount of current available from the drive circuit and the achievable switching time. With gate charge known, the designer can develop a drive circuit appropriate to the switching time required.

\$Q_g=C_gV\$ , and \$I_g=C_g dV/dt \ , \ Q_g=I_g*dt*V/dV = I_g*dt\$

or \$dt =Q_g/I_g\$

Since the gate impedance is dominated is basically a capacitor between gate & drain similar to Miller capacitance and series gate resistance. Also the drain voltage transition dV = Vd which is the is initial drain voltage being drained, these cancel.

However the Miller Capacitance is nonlinear.

enter image description here

They cannot show every scenario of Vgs , Vds and Id but the “bottom line” importance is the total gate charge required for switching. The gate drive current depends also on Vgs slew rate but for this test curve a constant current source to both gate and drain is used.

A lower drain current implies a shorter gate time interval for the peak gate current if voltage source. But a low current gate source and low drain current load implies a much longer transition time. A voltage source with a low drain current implies a high gate current for a much shorter time.

The initial Ig current of turn-ON is Qgs until threshold Vth is reached then Vgs remains constant ( since source current Id is now active and is constant) with a gate test current source controlled by Qgd as Vds drops to RdsOn*Id next Vgs rises to max from dV/dt=Ig/Cg. So the test circuit uses a switch to activate a current source to the MOSFET Gate then a drain current source to record the Gate Charge curve.

E.g you would not choose a 1 millohm FET to switch 5mA load with a voltage source because the gate current could be more than an Amp due to Cin with a fast dVg/dt. RdsOn and Cin (Ciss) products (T=RC) are somewhat of a constant in a given MOSFET family and a common figure of merit, (FoM) for comparison. but the bottom line is Qg*RdsOn.

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Tony Stewart EE75
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  • While this is well written it is not an answer to either question in the OP. Common sense and your wording of VDS being "drained" tells me that the Vds=80V label refers to VDS before switching, not after, which hopefully is the answer to my first question. Please correct me if I'm wrong. The graph in your reply shows that the max ID has indeed an effect on the total gate charge at full VGS. How should I approximate total QG if maximum Id is only 1mA in my case? – JMC Jan 09 '17 at 02:31
  • in my last chart if you supplied 10V with 0 ohms to 20nC in 10ns the gate current could be 2A . thus practical drivers become current limited and 2 or 3 stages of RdsOn reduction are necessary go from 1k to 1mOhm. In any case your charge is too large Q or not relevant for a 5mA application – Tony Stewart EE75 Jan 09 '17 at 03:43