3-state buffer mechanism

Question

I read about the 3-state buffer. I do not precisely understand the working mechanism. It allows essentially to obtain a third state, that corresponding to the disconnection of the output from the circuit (eg. a bus).

This disconnection of what exactly it consists?
In what sense the corresponding Z high impedance state differs from the standard state 0 of ordinary output?
Can we get a complete absence of current, when the buffer is active?
If this is the case, how can that result be reached?

score 7 · Accepted Answer · answered Dec 09 '16 at 08:10

A typical output stage uses a totem-pole or push-pull configuration. For a logic 0 the lower transistor is on for a logic 1 the upper one.

Now it is possible to turn off both transistors which neither drives the output high or low. The circuit is basically disconnected (high impedance, high-Z).

A circuit that accomplishes that is shown below.

When enabled the signal QP12 and QN12 are on the inverter formed by QP11 and QN11 can drive the output.

In the disabled state QP12 and QN12 disconnect the inverter from the supply and the output is in a high impedance state regardless of the input signal.

So the result is absence of current. It is just like someone had cut the wire. — Bento, Dec 09 '16 at 08:33

3-state buffer mechanism

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