How is a high avalanche ruggedness physically achieved for a MOSFET and what are the trade-offs in other parameters to get a high avalanche rating. Also, how should one interpret the avalanche energy listed in the datasheet? Another way to state this may be, for a given design, how do you know how high a rating you will need? Thanks.
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Good ones come with both single and repetitive avalanche ratings. What's the circuit you need to avalanche? Can you use a zener in parallel? – winny Nov 22 '16 at 17:53
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We had a problem with the output stage of a motor driver wherein the low side FETs were turning on very slowly and causing repetitive avalanche which eventually failed the FET. The solution to the problem was to correct the gate drive issue, not ruggedize the FET, but seeing the problem got me thinking. I have seen FETs that are specifically advertised as avalanche rugged. – walkingcrane Nov 22 '16 at 19:20
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Turning on very slowly does not cause it to avalanche. For that you need higher SOAR. – winny Nov 22 '16 at 19:48
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This not really part of the original question, but to respond to your comment, the turn on was extremely slow so it was not about SOA really. It was about motor current built up to a high level and then having no path out so the voltage at the low side drain built up and avalanched the FET. Turn on was taking microseconds, including several hundred nanoseconds alone in the plateau. – walkingcrane Nov 22 '16 at 20:44
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Oh! That's a complicated issue. Unless you need very low output capacitance/high switching frequency, I would still suggest a zener diode. It's purposely made to go into avalanche. – winny Nov 22 '16 at 20:47
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This topic can go very deep! I'll try to say a bit about it, according to my understanding, to at least get you started.
Power FET manufacturers began advertising their transistors as "avalanche rugged" in the mid-80s. While there was - and still is - some confusion as to what this means, many modern power FETs have a degree of robustness in the face of avalanche conditions.
Physically, avalanche robustness is achieved by preventing the mechanisms that would otherwise degrade or destroy a FET under breakdown. The two that I am aware of are snap back and hot-carrier injection. When a FET experiences snap-back, it essentially turns itself on under breakdown and can't easily be turned back off, resulting in destruction. Hot-carrier injection is a phenomena which can degrade a FET or alter its characteristics over time, even if it doesn't go into "deep breakdown". The phenomena is, again, a fairly complex one, but basically high energy carriers are generated in the drain depletion region and - if they are close to the gate - can actually penetrate the gate and impregnate it with permanent charge.
Both of these phenomena can be avoided if the breakdown current is made to run through a safe path where it doesn't generate problematic hot carriers near the gate, and doesn't activate the parasitic snap-back BJT. An avalanche rugged FET don't snap back, so for VDS above their avalanche rating, it acts a bit like a TVS diode. This is achieved physically by altering the doping profile of the backgate or adding an auxiliary drain-body diffusion that is designed to run substantial current without thermal hot-spotting issues and without activating any parastic BJTs. As for the design trade-offs, I am not expert enough to say - my guess is that it adds die area and perhaps additional parasitic capacitance.
When a rugged FET avalanches, VDS will clamp near the breakdown voltage. Any current that runs through the FET at this time will result in significant power dissipation (ID*BVDSS). But often, power supply designers only need to break the FET down for a short time. This situation comes about, for example, when there is residual energy in the inductor of a switching mode power supply after a switching event. Designers can calculate the energy in the inductor that needs to be dissipated, and datasheet curves allow them to calculate the junction temperature rise that will result. As long as the transistor can tolerate the energy delivered to it in breakdown without thermal issues, then it can survive even periodic breakdown events.
In case it is not clear, this about surviving in the face of transient avalanche events, NOT DC avalanche conditions.
Materials from FET vendors will give you a better practical guide of how to interpret data-sheet curves and design for avalanche. I recommend the following two white papers:
user49628
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High Voltage devices need to absorb their energy, in place. I'd expect the 10 micron junction depth to be about right, thus 1.14uS is a survival-time prediction for high current density in an avalanche pulse.
Silicon has computable thermal timeconstants.
1micron^3 is 11.4 nanoseconds
10micron^3 is 100*11.4 nanoseconds or 1.14uSec
100 micron^3 is 100*100*11.4 nanoseconds or 114uS
1,000 micron^3 is 100*100*100*11.4 nanoseconds or 11.4 milliSeconds. This is 1millimeter, probably 3X the typical wafer thickness.
ESD structures survive by moving the ESD energy deep INSIDE the silicon. Are avalanche structures the same? Heating the bulk permits the heat to flow in TWO directions, instead of just one if the surface has to absorb all the energy.
An unthinned wafer at 300 microns will have 1.14 milliSeconds Thermal Tau.
analogsystemsrf
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