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I would like to simulate a simple one-bit counter (or frequency divider) using the D-flip flop.

1-bit counter / frequency divider

However, I don't want to use the abstracted D-flip flop above. Rather, I want to simulate this using primitive NOR/AND gates directly. I rigged up a D-flip flop based on NOR Gates below.

The full simulation can be seen at this link: http://tinyurl.com/z6mae9c

However, I cannot connect the Q' output back into the "D" input without getting an error (endpoints circled in red below). Can anyone recommend how to fix this? Is this a limitation of the simulation framework? If so, what's a good package to simulate this on?

enter image description here

Ismail Degani
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http://tinyurl.com/zonbe7q

It cant work as you expected, but I fixed the simulation

Difference between latch and flip-flop?

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Tony Stewart EE75
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  • Thanks a lot Tony, the link was very helpful! I was able to finally construct a working frequency divider using the master/slave flip flop design: http://www.falstad.com/circuit/e-masterslaveff.html – Ismail Degani Nov 18 '16 at 07:47