Using string type in VHDL

Question

To make it easier to read a waveform in the testbench, I want to use a signal/variable that is of string type. Basically e.g when I am reading address 0x03 from an SPI device, the string shall say that in words until the SPI transfer is complete.

This will make it easier to read the wave output.

Problems:

1) String variable/signal must be given bounds when it is created. Unlike C++ it does not seem to internally expand/contract to fit what is assigned to it at run-time. This should be possible for an aggregate.

2) Cannot use (others=>'') notation with string type even though it is supposed to be an array.

3) Sometimes I have a string returned from a different function that needs to be concatenated with the msg in the testbench. If I have to enter bounds for the string when I assign it value, this will become impossible.

Is there a way to use a string without assigning bounds in VHDL? Atleast can I assign value to a string such that if my assigned string is less than max bound, the rest of the string shall be set to space characters automatically?

For a testbench there's textio lines or Kneiser, Wolff and Papachristou's big-endian stdio_h package in VHDL (under GPLv2, uses textio line, access (pointer) to host memory). Synthesis eligible hardware is tough requiring barrel shifters for all the possible starting concatenation points and all the possible lengths. The classic way is to justified parallel load a shift register and serial shift by length, a time and space trade off requiring memory word width framing and word counting, the mechanism is used for HW variable length codes. Draw a hardware block diagram. — , Oct 30 '16 at 05:02
thanks for the input, I only intend to use the variable length string in the waveform window. However, I have always wondered what purpose the string type could have in synthesizeable hardware. — quantum231, Oct 30 '16 at 12:12

Lincoln · Answer 1 · 2018-04-09T13:24:27.920

I think you really want an enumerated type. They will show up named in the simulation without the hassle of strings. You will need to check them out to figure out completely how to use them. Here are the basics:

-- declaration   
type my_enumerated_type is ( good, bad, ugly);
signal rating, rating2 : my_enumerated_type;
constant ENCODED_TYPE_WIDTH : natural := 2;

-- helpers - use a function like this to convert between enumerated type and std_logic_vector
function encode ( rating : my_enumerated_type ) return std_logic_vector is
begin
  return std_logic_vector(to_unsigned(my_enumerated_type'pos(rating), ENCODED_TYPE_WIDTH));
end encode;

function decode ( rating : std_logic_vector ) return my_enumerated_type is
begin
  if unsigned(rating) < my_enumerated_type'length then
    return my_enumerated_type'val(to_integer(unsigned(rating)));
  else
    return ugly;
    -- TODO: throw an error instead? like so: 
    -- assert false report "rating out of bounds in conversion to my_enumerated_type" severity ERROR;
  end if;
end decode;

-- conversion
output  <= encode(rating);
rating2 <= decode(input);

These enums can be fun and powerful in VHDL. Enjoy!

Using string type in VHDL

1 Answers1