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I want a 500uF capacitor. Theoretically, I should be able to place 5 100uF capacitors in parallel to achieve 500uF of capacitance.

However, are there any side effects of practically implementing this? Are there non-ideal effects that I should account for?

Note: I'm looking for a 500uF surface mount ceramic capacitor. I've been able to find these, however, the tolerances are only +/- 20%. Furthermore, I've only found one manufacturer of these and I would prefer not be too dependent on a single manufacturer.

Izzo
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  • Resistance of the wires, some current loops. – Eugene Sh. Oct 28 '16 at 15:30
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    What are you doing with a 500 uF cap that 20% tolerance is a problem? – The Photon Oct 28 '16 at 15:34
  • @ThePhoton Pulse powering via a battery. I'm trying to maintain low current draw from the battery, and I have a very time specific power period. Which I suppose 20% extra is fine, but 20% less isn't. – Izzo Oct 28 '16 at 15:35
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    Then make it 600 uF so that 20% less is acceptable. The problem is not with the 500 uF cap, but with your spec. – Olin Lathrop Oct 28 '16 at 15:37
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    @JRE: No, the inductance goes down too. Multiple inductors in parallel is *less* inductance. – Olin Lathrop Oct 28 '16 at 15:38
  • @OlinLathrop Can't seem to find one. – Izzo Oct 28 '16 at 15:39
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    @Teague, use two 470-uF caps, or 3 220-uF caps, or one 680-uF. Or 10 100-uF caps. This isnn't sound like an application where you can have too much capacitance, only too little. – The Photon Oct 28 '16 at 15:51
  • @ThePhoton Noted, and I will likely do that! – Izzo Oct 28 '16 at 15:56
  • Most common practice is to have 2 at least good caps which span 3 frequency decades of useful shunt current, sometimes 3 caps are needed. other times 30 parallel wide aspect ratio low ESL ceramic SMT caps are preferred for sub millohm ESR. , but typically people used e.g. 1000uF , 1uF , 1nF for example with high pulsed current loads. BUt beware modern ultralow ESR MOSFET LDO's become unstable with TOO LOW ESR caps due to lack of ripple feedback. – Tony Stewart EE75 Oct 28 '16 at 16:09
  • Solution is to compute ESR ratio of Battery to load. THis is called % load regulation ripple. where Cap ESR is part of source or load depending where it is. Load Regulation is given for any regulator. It basically defines the ESR of the source or battery in this case. But R(load)C must be much greater than pulse load duration and batteries have thousands of Farads equivalent C – Tony Stewart EE75 Oct 28 '16 at 16:12
  • for a "better" answer please define Battery part number, load spec Amp or Ohms and duration – Tony Stewart EE75 Oct 28 '16 at 16:16

5 Answers5

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Paralleling capacitors is fine electrically. That actually reduces the overall ESR and increases the ripple current capability, usually more so than a single capacitor of the desired value gets you. There is really no electrical downside to this.

The prominent non-ideal effects are cost and space.

Olin Lathrop
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Depending on the industry you are dealing with, dormant failure modes could be a consideration.

5off 100uF @ +-20% means you maximum spread of terminal capacitance is: 400uF --> 600uF. Sure what are the odds that all are at the maximum or at their minimum...

If one capacitor failed open-circuit (solder, mechanical etc...) the total span is 320uF --> 480uF. & the nominal range lies within this, dormant failure that is not quickly detectable during any production PAT's.

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Parallel capacitors can actually introduce resonance at high frequencies, especially if they have different values. See this link for more information. Especially the plot on page 3.

This is actually a big problem when decoupling BGAs as you cannot get the capacitors as close as you would like, and you need to use different values.

user110971
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    This might be useful information for a future reader, but probably doesn't apply to OP, since he's talking about a value that's most likely an electrolytic type (with higher ESR to reduce this effect) and not talking about combining different values. – The Photon Oct 28 '16 at 16:12
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    Yeah, I know. I just wanted to put it here for reference. – user110971 Oct 28 '16 at 16:31
  • Also, it depends how far the caps are. You have inductance on the traces. – user110971 Oct 28 '16 at 16:32
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Yes there is a huge penalty for ignoring ESR in parallel caps at RF frequencies.

Due to Resonant (//) and anti-resonant (series) behaviors in parallel caps, ultra-low ESR ceramic caps can actually amplify noise due to high series Q, even if parallel (//) Q is low.

Murata has championed this by raising the ESR a bit in their RF ceramic caps to reduce the Series Q and flatten the overall "low Z bandwidth" in SMPS filters, which becomes critical >1MHz switching rates.

You must be aware of ESR*C time constant in all shunt caps, SRF and Series Q as well for optimal ripple rejection of harmonics.

Proof:

How much resistance does the capacitor itself contribute to an RC circuit?

For more experience on ESR vs value of C, ref my info (which I can backup) What happened to electrolytic capacitors in the 21st century?

Community
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Tony Stewart EE75
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    500 uF is not likely to be an "ultra-low ESR ceramic". And nobody's mentioned combining different values, which is usually how anti-resonant behavior is found. – The Photon Oct 28 '16 at 16:07
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Your problem is not the ESR of the caps , rather it is the high ESR of the coin cell ( based on your previous questions)

Solution: Use a better battery such as CR123A with much lower ESR 3.00V <<1Ω ESR

Lithium primary cells have FAR more capacitance than electrolytic capacitors at same cost or size.

  • Load regulation error % drop in coin cell voltage = RL/(RL+ESR(bat)

Proof of ESR ( ignoring estimate tolerances from graph but for 50% SoC cell.)

Sample datasheet

enter image description here

  • Rule of Thumb
    • CR1025 has 30 mAh capacity at 0.1mA load and ESR of ~161 Ω
    • CR1216 has 25 mAh capacity at 0.1mA load and ESR of ~210 Ω

- thus Ah capacity is inverse to ESR of battery or mAh*ESR = constant - for given family for chemistry and supplier

  • exactly the SAME is true for any capacitor where ESR*C = constant
    • for any given family and similar size
    • but varies between internal chemistry, quality, supplier.
    • as cap or battery wears out ESR rises sharply and C drops sharply as mAh drops .
  • ESR*C < 1us for ultra-low ESR
  • ESR*C - 100us to >1 ms for general purpose alum electrolytic
  • ESR*C <0.01us for low ESR ceramic in small values.
Tony Stewart EE75
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