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I just need to create a logical circuit. i have input and output signals. Here is steps which i need to have done

  1. Simplify boolean expression using karnaugh map
  2. Generate logical circuit using expression from step 1 and different basis
  3. Generate time diagramm of working my circuit

Is there any software which could help me?

Neir0
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    What is your target device - CPLD, FPGA, or ASIC? How many inputs & outputs from your logic? – The Photon Feb 13 '12 at 17:01
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    @The Photon It doesnt matter. It is not a real device but just university work. – Neir0 Feb 13 '12 at 17:06
  • Seems like a homework; do wyou need to generate the karnaugh map from the truth table and then extract the circuit? You need a software only if the function is really complicated, or you have to do it in batch many times...otherwise is 5 minutes with pencil and paper – clabacchio Feb 13 '12 at 17:08
  • @clabacchio i need to do it in many times with 4*4 function and different basis – Neir0 Feb 13 '12 at 17:22
  • It's a so simple function that you have lost more time asking then solving it by yourself :) – clabacchio Feb 14 '12 at 08:31

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It seems to me that using software for such a task is somewhat defeating the purpose of the University assignment. Doing it with software, even if it does exist, is at best going to eliminate that part of your education and at worst going to put you at a disadvantage in later classes where you need to utilize this knowledge. Any time you save now will be completely lost later when you have trouble with future assignments.

I am assuming that using this kind of software wasn't the intent of your professor, otherwise he/she would have provided the software themselves (or a link to it).

Software for FPGA/CPLD/ASIC design isn't going to help you much, if at all. While they will do what you ask, the results are not going to be in a format that will be useful. To make matters worse, that whole "show your work" part of your assignment will be missing.

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Logic Friday is a good tool for logic minimization and gate diagram generation.

You can use Gorgeous Karnaugh to generate and minimize K-Maps. Also, it can generate logic gate diagrams.

CedarLogic simulator can simulate logic gate diagram and builds time diagram, but has some bugs and often crashes.

All tools above are very simple and not too hard to understand its, in difference from professional tools.

kruz05
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For generating Karnaugh maps, check this question.

When you have generated your K-map, it's just about choosing the logic to implement it (sum of products or vice versa) and draw the circuit.

Then, if you want, you can simulate it with Falstad, any version of Spice, like LTSpice or NI Multisim (you'll have to pay for it.)

Community
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clabacchio
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LogicWorks is a great piece of software to lay out and test what you create. It wont automagically do everything for you, but once you make the K-maps you can use it to visually lay everything out and verify the design. Does timing maps too IIRC.

Kris Bahnsen
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Logism is a free, open-source, logical diagram simulator written in Java. I used it for my computer hardware class and it generates boolean expressions, kmaps, and truth tables.

bejazep
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