How to model I2C Bus in LTSpice?

Question

I want to model a single one master and two I2C Slaves on a bus. I want to determine how long I can make the I2C Trace to the last/second slave.

How to model the length of the I2C Bus in LTSpice? Should I be using a transmission line model?

This is an unusual goal for a simulation. For a more global picture of the problem, what bus length do you hope to achieve? — dim, Oct 12 '16 at 20:56
Probably this post may be of help, http://electronics.stackexchange.com/questions/106265/maximum-i2c-bus-length — Ale..chenski, Oct 13 '16 at 00:35

score 1 · Answer 1 · answered Oct 12 '16 at 20:46

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The length of the I²C bus manifests itself as capacitance, and you can model it as a lumped capacitor. The I²C bus (assuming typical short distances which it's intended for) is way to slow to be concerned with transmission line model.

answered Oct 12 '16 at 20:46

Nick Alexeev

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score 0 · Answer 2 · answered Oct 12 '16 at 21:13

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Unless you've got a ground plane with a capacitance which the trace works against, The length of the trace manifests itself as inductance, so if you have a problem with delay you should tune it.

answered Oct 12 '16 at 21:13

EM Fields

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score 0 · Answer 3 · answered Oct 13 '16 at 00:58

If you need to design your own I2C receivers and want to see now reflections might affect your sampling point, use of transmission line model is always useful and educational. For a fast mode (up to 3.4MHz) the reflections might chew up a significant portion of bit time.

How to model I2C Bus in LTSpice?

3 Answers3