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Should I guard a PLL loop filter against current leakage with a pour? If so, where can I connect the guard plane?

As an illustration: I use an IC in need of an external PLL-loop-filter connected to the charge pump (a MAX2769). The manufacturer recommends to use a C-R-C-network as follows:schematic (the DNIs are not installed, the installed caps are silver mica type from Cornell Dubilier).

As you can see, there is a 1M (or 100M?) resistor to a net called PLL_FILTER_FENCE. This network is used to pour a plane around the components like this:pcb This pour is intended to minimize current leakage from the components. As you can see, space does not allow for a plane that also encloses the IC pad. The plane will also introduce an additional filter pole which should not affect PLL performance.

Will this be helpful at all, as there is no low impedance source to connect the guard to?

Andreas
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  • What frequency is the PLL running? – user110971 Sep 22 '16 at 20:13
  • @user110971 It generates roughly 1571 MHz from 20MHz (fractional N). Charge pump current is switchable between 1mA and 0.5mA . – Andreas Sep 22 '16 at 20:17
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    okay. I need some more information here. Is the red layer the PLL_FILETER_Fence? How many layers is the PCB? What is the stack up? Do you have size restrictions? What tools do you have access to? – user110971 Sep 22 '16 at 20:23
  • @user110971 the bright red selection is *all* nets from the schematics except LD/ANTFLAG. The Guard is the pour connected to the leftmost 0402 resistor. I can upload another IMG if you have problems spotting it. The buildup is 4-layer I-Tera (http://www.eurocircuits.com/clientmedia/ecImage/Document/I-Tera-MT-RF-Very-Low-loss-Laminate-Isola.pdf). Size is not restricted, but "tiny" is desired. I do not use SPICE (yet). TNX – Andreas Sep 22 '16 at 20:31
  • okay. I'll think a bit about it, but my first reaction is that I do not like it. Why are you worried about leakage, and where is it going to leak to? What do you actually mean by leakage? Do you know what are the waveforms that are coming out of the charged pump? Or if not, the frequency of the charged pump? I think I'm also noticing some other problems. Do you have a continuous plane on the layer adjacent to the red layer. It appears there is a gap. Finally, do you have frequency response data, i.e. S-parameters, for the 1M resistor? What is its impedance like at MW frequencies? – user110971 Sep 22 '16 at 20:44
  • @user110971 MAXIM recommends to use low microphonics low leakage caps. I wondered if a guard would make sense. I use that in other places, f.e. Linear recommends it for [this LDO](http://cds.linear.com/docs/en/datasheet/3042fa.pdf). It may be nonsense after all, thats why I ask. I do not know what waveform to expect in the CP. The ground plane is solid/unbroken except for vias. The laminate is only 10mil to facilitate tuned impedance traces. I did not care about resistor impedance up to now, passives selection is a pain anyway, isn't it? – Andreas Sep 22 '16 at 21:03
  • it makes sense for the LDO because you are trying to protect the pin in the middle, which is quite sensitive. They are trying to prevent a current interference of 100nA or so. I have enough information now. I'll write an answer. – user110971 Sep 22 '16 at 21:10
  • Everybody remember, just because the PLL generates 1571 MHz, doesn't mean that frequency is present on the VCO control signal. More likely, the frequencies there are somewhere below 10% of the reference frequency, so 2 MHz or lower. That said, this guard ring looks pointless, since it isn't providing a lower impedance path for leakage currents. – The Photon Sep 22 '16 at 22:19
  • @ThePhoton that is what I thought, and is the reason why I asked for the spectrum of the charged pump. In all likelihood the charged pump is far slower than the PLL output. Nevertheless, when you have GHz signals elsewhere in your board, the floating copper pours can form resonant cavities and couple to them. Or there can be resonance on the ground plane that in term resonates with the copper pours. MW signals have a nasty habit of getting where you don't want hem to be. – user110971 Sep 23 '16 at 09:10

1 Answers1

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Don't do it. The 1M resistor will have a significantly reduced impedance @ 1.5Ghz. Even if that were not the case, the floating pours can become really good antennas @ 1.5 Ghz. Think about what a patch antenna is: a trace to a copper pour. The resistor is trying to prevent this, but it can still resonate with adjacent signals.

I have worked with frequencies that are similar to yours. Here is what a typical design process is:

  1. Layout the board
  2. Do signal integrity on the fast signals
  3. Get the S-parameter models of your decoupling capacitors
  4. For each IC compute the impedance to ground from the power pins using FEM
  5. Add capacitors in the simulator in order to get your target impedance
  6. Add the capacitors to the layout, go to 4 and repeat until step 5 is satisfied
  7. Use FEM to compute the resonant modes of the planes
  8. Add capacitors to suppress them
  9. Add capacitors to the layout, go to 7

As you can see, doing the signal and power integrity at such frequencies is not a trivial task. You can end up with 1000's of capacitors. You will probably be okay, if you follow the layout recommendations of the manufacturers. Just remember, a floating plane is an antenna, if it happens to resonate at a frequency that is present on your board.

Decoupling at Ghz frequencies is not easy at all. Here is a typical impedance curve: decoupling Note how the capacitors become inductive. That is why you need to combine high values with low value capacitors. But it is not as easy as that, because the different valued capacitors can start resonating with each other. Always make sure you use the recommended capacitor part numbers from the manufacturers in the specified package sizes, if you are not able or willing to carry the level of analysis I have outlined.

user110971
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  • That sounds like good advice. I will wait if I get other opinions, then accept. I did check SRF on capacitors and I also had problems to find a suitable one in some occasions. But I did not go to such great length to assess the design. My doubts about that plane were also about floating, I usually try to avoid islands and fins with vias to ground, but I did place them without doing much analysis. – Andreas Sep 22 '16 at 21:43