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We have power traces in inner layer (the yellow traces). We have linked all our nets with traces taking care of track width based on current flowing into the nets.

Now, we are wondering if we should keep this like this or if we should create a polygon for each track (which I suppose might be benefical to spreading flow over a larger surface).

What would you do ? Would you create polygon and if yes how would you draw them to make them adjacent to each other and to delimit their borders ?

enter image description here

chris
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  • I'd go with polygons for at least the higher current traces if not all of them. Also for some of those high current paths you may want to look at using multiple vias rather than just a single one at each point. – Andrew Sep 13 '16 at 09:13
  • @Andrew thank you for your comment. This is what I saw thinking. i suppose I should use the split plane methodology and not the polygon tools to perform this? – chris Sep 13 '16 at 09:17
  • With that many small areas I'd go with polygons, keep each signal within the region that it's relevant. – Andrew Sep 13 '16 at 09:20
  • How high are the currents? – Bence Kaulics Sep 13 '16 at 09:22
  • @BenceKaulics from 5mA to 2A (for the 50mil width track you can see called SYS) – chris Sep 13 '16 at 09:30
  • @Andrew if use polygon, how do you define the shape of the polygon apart encompassing the track and do you manage the clearance between polygon ? This is actually my real question. Do you do this manually with estimation by eyes or you use some design rules to perform this ? – chris Sep 13 '16 at 09:32
  • Use the *polygon* plane tool to draw polygons. – Voltage Spike Sep 13 '16 at 15:39
  • @laptop2d how to decide the shape and spanning on the pcb of the polygon ? Do we have to fill whole pcb ? – chris Sep 13 '16 at 18:57
  • @chris Have you tried experimenting with the tool? It's intuitive and like drawing polygons in many other programs. You get to specify the vertices. – Voltage Spike Sep 13 '16 at 19:12
  • @laptop2d my last remark is not about drawing but about zoning. I know how to draw polygon and how to separate them. My question is about how to decide if I should cover whole pcb surface area with a +3.3V polygon for example or not... – chris Sep 13 '16 at 19:14

2 Answers2

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I would go with polygons for 2 reasons:

1) More copper = more area = less thermal problems due to current heating up the copper.

2) By filling the entire layer with copper, regardless PWR or GND, you are reducing the gaps that the prepreg can flow into when the fabricator presses the layers together. This helps keep things mechanically stable and ensures an even thickness of prepreg across your board.

Here is a useful calculator for calculating required trade width given copper thickness, current, and temp rise: http://circuitcalculator.com/wordpress/2006/01/31/pcb-trace-width-calculator/

FullmetalEngineer
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To answer your first question regarding the polygon usage. It depends on the amount of current flowing in the signal. It is generally advisable to use polygon if lot of pins/pads are connected on same net, as the area is fairly larger and more current can pass without heating(?). Veterans and experienced users can throw more light in this perspective.

Now the question regarding how to manage polygons. The answer is strictly limited to Altium Designer.

To define a polygon; you can open the Polygon Manager(Option Available in Tools) and create a polygon and connect it to a net.

When you create a polygon; it will ask you to draw a shape; you have to enclose the targeted area. This will create the polygon.

For a graphical representation of what i just said : LINK

Skip to Polygon Pour section.

Now to polygon clearance; this is tricky in Altium as the Design Rules are overwhelming for beginners (like me)

For starters : Look at this answer by connorwolf :LINK

This is the exact problem i faced when designing boards in altium and it took my some time to figure it out.(I got it through altium documentation though)

Another Link from University of Florida explaining Polygon Rules in Altium : Link

I hope this answers your question.

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ammar.cma
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  • does the whole surface of poiwer plane should be fill with polygon of power ? I see some design where the pcb designer fill the whole surface of the pcb with power net but i also see some other where they fill with trace and fill the power plane remaining area with ground. SO I am confused; – chris Sep 13 '16 at 15:38
  • @chris Filling planes is up to the designer, it has to do with PCB parasitics, realize that a PCB has resistance in the copper and the insulator. Inductance in the copper and capacitance in between planes. There are plenty of PCB books out there, I'm not going to recommend one because everyone is different. A good design book however is Electromagnetic Compatibility Engineering by Henry W Ott – Voltage Spike Sep 13 '16 at 19:16
  • It is upto the designer as suggested by @laptop2d; although i prefer the pour the copper on the maximum number of pads in the proximity of pour. – ammar.cma Sep 14 '16 at 09:12