Write back buffer in lpc

Question

I was reading the Lpc2148 Manual and in the Static Ram section I came across

Write back buffer

The SRAM controller incorporates a write-back buffer in order to prevent CPU stalls during back-to-back writes. The write-back buffer always holds the last data sent by software to the SRAM. This data is only written to the SRAM when another write is requested by software.(the data is only written to the SRAM when software does another write). If a chip reset occurs, actual SRAM contents will not reflect the most recent write request (i.e. after a "warm" chip reset, the SRAM does not reflect the last write operation). Any software that checks SRAM contents after reset must take this into account. Two identical writes to a location guarantee that the data will be present after a Reset.

What does it mean. and what did he mean by CPU stalls and back to back writes

Answer 1

The write-back mechanism is a method usually used to guarantee the consistency of the data in memories in a multi-agent system (multi-core systems but also with DMAC - controller of hard disks - for instance). In this case is meant to avoid writing data in the RAM in case it's required in short time from the CPU.

It means that the data is not immediately written to the memory, but held in a register until anyone requests it. It's the alternative to the write-through policy, in which every time a write-to-RAM instruction is called for data, it's written directly to the RAM.

It prevents CPU stalls (that are clock cycles in which the CPU is waiting) because the result of the instruction is saved in the register for future access, and it's written to the memory only if needed (another "write" instruction requesting the buffer, that has to be emptied); so you don't need to save into (and load from) RAM a value that is requested in the next instruction.

In this way the content of the RAM is not always up-to-date, so it shows a trick to guarantee that a certain data is written before a reset.

Answer 2

The top writing speed of the CPU is higher than the SRAM can handle. This can be solved by stalling (halting) the CPU untill a write is completed, but this would slow the CPU down. Instead the write action can be stored in a buffer and handled by the SRAM at its own speed. The CPU can now continue executing instructions. Of course the CPU must still be stalled if it attempts a next write action before the write buffer has been written to SRAM. (Instead of a single entry the write buffer can be a queue. Reads actions by the CPU must of course check whether they are reading an address that is in the write buffer or queue.)

The ARM7 seems to use a single writeback buffer, but the text in the manual is not 100% clear about when the actual SRAM write occurs. It suggests that it occurs only when a next CPU write takes place, which would IMO be silly: its only profit would be to eliminate a second consequtive write to the same address with the same data.

CPU stalls == halting the CPU because it must wait for something to complete before it can continue. 'Something' can be many things, like memory read or write, internal (pipelined) operation, result of a previous operation becoming available, etc.

back to back writes == in this context is seems to mean two consequtive writes to the same address.