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The schematic of a SR flip-flop is the following:

enter image description here

The equation for the output is:

$$Q^{t+dt}=(S+\bar{R}Q)^{t}$$

What I don't understand is that as the output \$Q\$ is given again as an input and the same happens with the \$\bar{Q}\$, doesn't this create a race condition?

jbord39
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Adam
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  • That's a SR latch with an enable pin... – Bradman175 Aug 24 '16 at 00:00
  • @Bradman175 My book uses the two terms interchangeably. – Adam Aug 24 '16 at 00:02
  • Well the actual definition between latch and flip-flop is pretty vague so you're not wrong. I'm just saying that this has slightly different capabilities compared to a true edge triggered flip flop. – Bradman175 Aug 24 '16 at 00:09
  • @Bradman175 I know and you are right but the question is pure theoretical and I don't talk about an actual electronic part. – Adam Aug 24 '16 at 00:11
  • Anyways trying to figure out the race condition. Gotta to do with timing. – Bradman175 Aug 24 '16 at 00:11
  • @Bradman175 I don't want to find the actual race condition I just want to see if there can be a race condition. :P – Adam Aug 24 '16 at 00:15
  • Checked it. It's possible, but it depends on the two end NAND gates and their delay (I think it's called slew rate). If Q is off and you have SET on and then the clock turns high, Q will go on first, making Q and Q' the same value before Q' goes off. The delay from Q turning on to Q' turning off is dependent on the delay of the bottom right NAND gate. I believe real SR clocked flip flops have a way around this. This is just a learning example assuming there is no delay in the ICs. (And I believe a consideration like this is in university level). – Bradman175 Aug 24 '16 at 00:20
  • This is a volatile memory cell.,So the initial state is can be either state and is normally initialized. Note that the crossed paths form a positive feedback loop thru two inverting gates,which is the stable condition for any latch circuit. Thus latches could be made similarily with NAND, NOR , AND OR gates. if you had to... – Tony Stewart EE75 Aug 24 '16 at 01:04

2 Answers2

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On startup, there is a race condition between between Q and Q' settling. Also, if both S and R are simultaneously toggled active, there is a race condition and invalid state. However, in normal operation, a race condition is pretty rare.

The case in which there could be a race condition during normal operation (only S or R is active at a time) is when the S or R active edge is not held long enough (minimum pulse width is violated) for the outputs Q and Q' to properly settle. In this case, there will be a race between the Q/Q' which is propagating through the feedback loop to stabilize the system, and the inactive edge of S or R (whichever caused the toggle).

jbord39
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This question has been answered here!

There is indded a race condition in the begining. Once in initial stable state is reached then there is no race condition anymore.

Community
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Krauss
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