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Well I'm designing a PCB with SPI comunication between a mastar and slave. My question is about the SCLK trace. Does it Has to be the same length as MOSI and MISO traces? It is clear that the last two have to be the same length but I'm not really sure about SCLK.

I will be very grateful if anybody can help me.

Nick Alexeev
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Didac Coll Pujals
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1 Answers1

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Consider this: -

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Outward bound from master to slave (left to right) - MOSI and SCLK should have delays that are preferably identical but this isn't the fundamental problem with SPI.

When it comes to inbound data via MISO (from a slave) you witness the fundamental problem with SPI because, the master is clocking-in MISO data synchronous to its local SCLK but, the slave is clocking data out against a delayed version of SCLK due to the length of the wires/traces.

Added to this is the delay incurred by MISO data getting back to the master from the slave. So you have: -

  • The delay (t\$_d\$) in the slave receiving SCLK. This causes the slave to output data onto MISO at time delay t\$_d\$
  • The delay in the slave data reaching the master (another t\$_d\$)

If those two delays add up to the half the time period of the SCLK clock then it all fails. If SPI clock is running at 20 MHz then half the period is 25 ns and therefore the line/trace delay should be significantly less than 12.5 ns.

A delay of 5 ns is approximately equivalent to 1 metre of 50 ohm cable just to put it into context so, you'd have to really try hard purposefully to make out-bound transmissions fail by totally mismatching line lengths.

Thus, outbound data is always going to be a winner compared to slave in-bound data. And, no matter what you do, accumulated time delays can cause in-bound data to fail if the clocking frequency is too high.

Having said all of that, do try and keep tracks/traces/lines as short as possible because at some point transmission line effects will also defeat SPI due to reflections.

Andy aka
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    Nice answer. Maybe break "That is two delays and if those two delays add upto the half the time period of the clock then it all fails." into two separate sentences; convert the 'and if' to '. If'? I had to read the whole sentence twice. Otherwise, lovely, especially the last sentence. – gbulmer Aug 18 '16 at 10:41
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    You should put some numbers on this, lest someone think it is a real problem for the typical project, which it is not! – Scott Seidman Aug 18 '16 at 10:45
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    @ScottSeidman OK example added! – Andy aka Aug 18 '16 at 11:03
  • @gbulmer OK hopefully made clearer! – Andy aka Aug 18 '16 at 11:03
  • Maybe I should have much more confidence in my fellow-human and their calculators. Maybe give the result of the example calculation, with something like 'A delay of 5 ns ... 1 metre of 50 ohm cable, so 12.5ns is about 2.5 metres of cable, just to put it into context', and maybe even, 'and so that is not an issue for this sort of speed SPI across a PCB'? (It does feel a bit 'Darwin award-ish', i.e. anyone who can't be bothered to do the arithmetic ..., but it might generate needless comments without extra clarity, because I think SPI is pretty popular). However, I think it is good as it stands. – gbulmer Aug 18 '16 at 11:19
  • I can't understand this sentence: "make out-bound transmissions fail by totally mismatching line lengths.". can you explain more? – mohammadsdtmnd Apr 09 '19 at 12:52
  • @mohammadsdtmnd if you wanted to make outward transmissions to a slave fail, you could do so by totally screwing up the track lengths of data and clock. It would be hard to do (and pointless of course) but compared to the return slave response being faulty, this could happen despite clock and data track lengths being perfect. – Andy aka Apr 09 '19 at 13:50