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i have a read out ic of optical front end which gives out digital pulse(0-3.3V) of width 10ns to 150ns repeating at a rate of 1Hz-70KHz

i have to measure the pulse width, but it needed a high end setup(high end FPGA like Arria from Altera costing 700$ ) which increases the cost a lot, so in order to go for low end pulse width measurement set up i.e. in my context a very low end FPGA(a cyclone-IV or V from altera costing 70$) which can run maximum at 100-200MHz clock , so i thought of expanding the pulse by a factor of 10

so my 10ns-150ns pulse would become 100ns-1.5us pulse, which makes me easy to measure the pulse width, by using a low end setup

but now my confusion is how to expand the pulse by a factor of 10 only ??? while i have in my previous project tried a comparator latches, which have a RC time to be programmed, but here the pulse width should not be made constant but should be replicated by a multiplication factor

kakeh
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    The Cyclone IV appears to be able to run a PLL past 1GHz. I don't know if you can get a counter to clock that fast, but what other option do you have? Surely magically multiplying pulse length is not a real thing. – Daniel Aug 09 '16 at 04:02
  • I am not sure how fast I/O can be on low cost Cyclone, but I tend to agree that sampling the 10ns pulse more than twice could prove rather difficult. You could consider converting the pulse from LVTTL to LVDS and acquiring it on LVDS. You would have to take into consideration the error of the converter... but I think it is a good alternative. Once on LVDS, you can enter at much higher speeds to the FPGA. You could also consider using fast single ended I/O on the FPGA like SSTL. – Claudio Avi Chami Aug 09 '16 at 04:09
  • @ClaudioAviChami i agree but , one has to see the cost of the solution also – kakeh Aug 09 '16 at 04:29
  • @Daniel i thought of this, using a dual triggerable MVB as configuration shown in page 12 (http://www.ti.com/lit/ds/symlink/sn74lv123a-q1.pdf) then ANDing the outputs would give me (Tr-inputpulse) then i can reverse calculate and measure, my minimum resolution is 10ns if i operate at maximum 200MHz clock.this is better solution than looking for a single sample from a 10ns pulse – kakeh Aug 09 '16 at 04:32
  • @kakeh a LVTTL to LVDS converter has to be a fraction of the cost of the FPGA. Using a fast single ended I/O (if possible) has not additional cost at all. And low cost Cyclone support LVDS. – Claudio Avi Chami Aug 09 '16 at 04:35
  • Read Brian Drummond's answer here: http://electronics.stackexchange.com/questions/122926/very-high-speed-counter-around-1-5-ghz-to-2-ghz The linked paper talks about some deep voodoo with delay lines implemented in an FPGA. – Daniel Aug 09 '16 at 04:58
  • Is there's a way of knowing when the next pulse will arrive? Is the 1Hz to 70kHz something where there is another signal that may be used to prepare a circuit to integrate the pulse? – jonk Aug 09 '16 at 05:13
  • What resolution do you need? Even the relatively lower end Cyclone V variants can do SERDES RX at speeds up to 740Mbps. That would give you 1.35ns resolution while internally the clock would only run at 74MHz (assuming 10:1 deserialization). – Tom Carpenter Aug 09 '16 at 05:41

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Rather than doing this with brute force and a GHz-clocked FPGA, this sort of job is well suited for a so-called Time to Digital Converter.

The basic concept is to integrate the pulse in the analog domain, charging a capacitor to a voltage proportional to the duration of the pulse. Then sample the capacitor voltage with an ADC, discharge the capacitor (actively or passively) and repeat.

There are ICs that will do most or all of this for you, or you can build one from a a couple of fast op amps, an ADC and some passives.

will try to flesh this out further with examples/links when back at a real keyboard

pericynthion
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  • the pulses may come at any time, how will i know the sample time, when you say ICs being available are you speaking about sample and hold circuits ? – kakeh Aug 10 '16 at 02:44
  • waiting for the update you said – kakeh Aug 10 '16 at 11:25
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It is possible to add or subtract some time to a pulse, but to multiply the length with a factor is not possible.

If the pulse length is constant over the next pulses, you can measure the cumulative length of ten pulses and divide the result by ten to get more resolution using a slower clock for measurement of pulse length.

Uwe
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