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I need help in completing a task, I’m stuck on quite a few things. Since I’m very new to this topic on finite machines.

I’ve attempted the state diagram, state table, transition table, K-map values and the k-maps (Karnaugh - map) themselves. However, a lot of it is incomplete, because I don’t know how to continue.

Any hints or help is appreciated; I’m not asking for answers just guidance, I’ve tried for a whole week now but still failed to complete this.

You can read my task down below. And in my drawings are questions highlighted in yellow, showing where I’m stuck, or where I’m having the most trouble in figuring out a solution.

Task: Design a clocked synchronous state machine for a combinational lock with two inputs (X and Y) and one output (Z).

Input ‘X’ is used to initialise the sequence entry. Input ‘Y’ is used to enter the binary sequence to unlock. Output ‘Z’ will be turned on if and only if the binary sequence is entered in proper order after the initialisation and must remain on as long as X input remains high.

This combinational lock operates as follows. Input ‘X’ must have changed from low to high in the previous clock period and should remain high afterwards (Initialisation). Entry of first binary digit must be done before the next clock cycle starts and entry of the remaining digits is done on the subsequent clocks.

If a wrong sequence is entered, it will require re-initialising to start entering the correct sequence. enter image description here

My tables and drawings for this task:

State Diagram

State Table and Transition Table

K-Map Values

K-maps

UPDATE!

State diagram State table

State Table State diagram

Omuse
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    Before you go too much further, note that the timing diagram shows the code being enetered LSB-first on the Y input. Your state diagram is processing it MSB-first. – Dave Tweed Aug 04 '16 at 11:51
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    +1 for a great question. This is a prime example of how homework questions should be asked. – Vladimir Cravero Aug 04 '16 at 11:53
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    The 'fun' part with writing the decision table is that you have a sparse transition table; *most* possible edges in the graph are don't-cares! I've happily thrown such synthesis at automated compilers for all of my recent state machine work. . . – user2943160 Aug 04 '16 at 12:01
  • @user2943160: Yes, but that misses the point of the question, which is to develop a detailed understanding of what the synthesis tool is actually doing for you. – Dave Tweed Aug 04 '16 at 12:18
  • I think that the initialize state is unwanted for and wrong. Once you sampled 'x' as high, the next states shall immediately sample the correct (or not) 'y' sequence. Because of the initialize state you are missing the first 'y' value. – Claudio Avi Chami Aug 04 '16 at 13:56
  • @user2943160 As in 'don't cares' do you mean 'x'? That's good then and I'm still a little confused on how to fill in my transition table, would converting my states to binary be the right thing? Such as 0000 for lock, 0001 for idle and etc. – Omuse Aug 04 '16 at 15:25
  • @DaveTweed I see, so I should keep my binary code in its backwards order(LSB first) when creating the state diagram? Thanks for the tip. – Omuse Aug 04 '16 at 15:44
  • @VladimirCravero, you're spot on, excellent post from OP, have also +1'd, to be encouraged. – TonyM Aug 04 '16 at 21:31
  • @ClaudioAviChami I'm confused what the question is asking fow when its talking about "x has to go from low to high in its previous clock period. And how entry of the first binary digit must be done before the next clock cycle starts". So should I just keep idle going to the next statement unlock 1 with x=0, then unlock 1 goes to unlock 2 with xy = 11? – Omuse Aug 04 '16 at 22:36
  • First states: IDLE -> (x=1) -> UNL1 -> (xy = 11) -> UNL2 -> (xy = 10) ... etc – Claudio Avi Chami Aug 05 '16 at 02:55
  • This problem is a glaring case where it makes way more sense to think of the problem with a datapath in mind. In the abstract, it more or less exactly calls for a shift register and a comparator as its datapath. Sprinkle in some glue logic and control signals and then manage *those* control signals with a state machine. But I get that it's meant as an instructive exercise, and such hardware should "fall out" of synthesis through rigorous application of conventional sequential circuit design methodologies. Maybe it is meant to illustrate a case where bottoms up design is "the hard way." – vicatcu Aug 06 '16 at 04:16
  • @ClaudioAviChami Also (at least for completeness) your state diagram probably needs a way to remain in the Unlock state indefinitely if X remains high, right? For that matter, do you have all possible input combinations covered as outgoing edges from each state in your diagram (I think possibly not)? That is to say, technically each state should have XY=00,01,10,11 accounted for on an outgoing edge (even if that edge loops back to the same state). – vicatcu Aug 06 '16 at 04:22
  • @vicatcu Could you please explain this? My English comprehension is poor and its confusing me a lot with the state diagram "Input ‘X’ must have changed from low to high in the previous clock period and should remain high afterwards (Initialisation). Entry of first binary digit must be done before the next clock cycle starts and entry of the remaining digits is done on the subsequent clocks." – Omuse Aug 06 '16 at 05:59
  • @ClaudioAviChami Thanks. Just wondering where will x equal zero? since x needs to be 0 first then 1. – Omuse Aug 06 '16 at 10:37
  • @Omuse the way I read that statement is that input Y should be ignored until there is a 0->1 transition on the X input. Also, that if X has a 1->0 transition before a match is found, checking for a match is aborted. – vicatcu Aug 06 '16 at 21:54
  • @vicatcu Thanks, Now it makes sense. I updated my state diagram and state table above. – Omuse Aug 07 '16 at 09:51

1 Answers1

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enter image description here Here is a partial version of the table you need to make. There is 64 rows in total. You determine the Q3*(Q3+) and the others by thinking what is the next state if I am in the current state and looking at X, Y.

Take for example line 2 : Current state 0000(RESET) and X=1, Y=0 this means the next state is 0001 (UNLOCK). Also Z is 0 when I am in state 0000.

You then get the output logic for Q0* by taking all the 1s in your column Q0*. For example for now I have (\ means "not")

Q0*= \Q3\Q2\Q1\Q0X\Y + \Q3\Q2\Q1\Q0XY + \Q3\Q2\Q1Q0\X\Y + etc...

You can then most probably simplify this expression. You won't really be able to do Karnaugh tables because there is 4 states bit and 2 entries = 6 dimension. I suggest you use the cannonic method for the logic as I explained just before.

You can check here for more info : https://en.wikipedia.org/wiki/Canonical_normal_form

Yanik Richard
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