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I've been trying to interface LPDDR2 ram with my SOC but got confused as to how to connect the CA lines. Does anyone have any reference designs of LPDDR2 for me to go off of?

jack sexton
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1 Answers1

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LPDDR2 is more or less confidential and thus not much information is available on it.

If you have routed DDR, it is almost straight forward as there is no termination, you just have to connect signals between them. I'm currently working on a design with a SoC and a LPDDR2 and it was really simple about the schematic, but routing is a bit more challenging.

CA are address lines and should be routed straight (Controller's CA0 to memory's CA0, etc.).

Bit and byte swapping is clearly allowed with other type of DDR and LPPDR but for LPDDR2 some note and appendix in the Jedec standard seem to not allow it. After looking for, some guys on Xilinx forum tried it and it worked fine, I also asked two LPDDR2 supplier and the SoC supplier (for the controller side), what is possible about bit and byte swapping:

  • Group 0 (DQS/DQSn0, DQ[0...7], DM0) should be routed straigh without swapping to allow support of Mode Register function (but it doesn't seems to be really used)
  • Group 1 (DQS/DQSn1, DQ[8...15], DM1), Group 2 (DQS/DQSn2, DQ[16...23], DM2) and Group 3 (DQS/DQSn3, DQ[24...31], DM3) can be swapped
  • DQ bit inside a same group can be swapped. But you can't swap a DQ from a group with a one in another group (i.e swapping DQ9 with DQ12 is OK, but swapping DQ9 with DQ25 is NOK)

Also with turn to the 168-ball PoP package which is clearly easier to route in 32 bits than the 134-ball package. But it will also depend of your PCB manufacturer and assembly as the pitch is very fine (0.5mm and 0.65mm).

You can read some recommendations:

But the best will be to contact a LPDDR2 supplier and ask him for help in your design.

zeqL
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  • This is the problem, my SOC does not have pins called 'CA' they have the generic ddr pins so it's confusing to figure out where to connect to on the SOC side. – jack sexton Aug 03 '16 at 23:25
  • Do your SoC's memory controller support LPDDR2 ? I'm using a Cyclone V and from the pinout file which show DDR2/DDR3 and LPDDR2 pins, for address LPDDR2 CAx are connected to DDR2 Ax pins, and BAx pins are not used with LPDDR2. RAS, CAS and WE are not used with LPDDR2 and thus are NC. ODT signal are still present on the LPDDR2 controller. A pinout file of Altera Cyclone V (XLS file) : https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/dp/cyclone-v/5cseba2.xls – zeqL Aug 03 '16 at 23:37
  • Here's my datasheet, it does support lpddr2. They are a chinese company so communication is very hard with them and datasheet lacks information. (https://www.dropbox.com/s/ci7kj329nggb15v/Allwinner_H3_Datasheet_V1.2.pdf?dl=0) I've seen alot of configurations like the one you've described for LPDDR2, is this some sort of default configuration? – jack sexton Aug 03 '16 at 23:39
  • Also how do you tell the SOC in your layout that you have interfaced with LPDDR2? Does the mem controller automatically detect this? – jack sexton Aug 03 '16 at 23:46
  • From the datasheet I don't see any problem : they just add a "S" before every DDR signal name. So use the Altera's pinout to use the correct DDR2 signals for LPDDR2 and it will be fine. Ask your LPDDR2 supplier for information and schematic review, I think your doing a real product so you have some volume, so support is inherent. For the SoC and LPDDR2, I don't know as we use a FPGA we configure it for LPDDR2. You may have to configure some boot registers / boot pins. Or it may be automatic, I really don't know. Ask them even if it's bad english, it's their product. – zeqL Aug 03 '16 at 23:52
  • Ok then, thanks for the help. I'll keep poking them. – jack sexton Aug 04 '16 at 00:05