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I am using a case statement in VHDL where the expression is a 12 bit bus address and the output is a 32 bit data bus.

Here is my code:

process (iAPB_BUS_IN.pclk)  
begin
  if rising_edge(iAPB_BUS_IN.pclk) then
    if (write_pulse = '1') then
      case bus_addr is
      when TX_CTRL    =>        
          rd_data(31)             <= tx_enable;
          rd_data(30)             <= arb_suppress_mgmt;           
          rd_data(29)             <= arb_suppress_2022;           
          rd_data(28 downto 0)    <= (others => '0');

        when TX_STATUS    =>
          rd_data(31 downto QUEUE_NUMBER)   <= (others => '0'); 
          rd_data(QUEUE_NUMBER -1 downto 0) <= tx_que_avalb;

        when RX_CTRL    =>
          rd_data(31)                       <= rx_enable;
          rd_data(30)                       <= rx_allow_tcp;
          rd_data(29 downto 0)              <= (others => '0');
        --------------------------------------------------
        -- What happens if I add another expression below?
        --------------------------------------------------
        when RX_CTRL2    =>
          rd_data(31)                       <= rx_que;
          rd_data(30)                       <= rx_allow_udp;
          rd_data(29 downto 0)              <= (others => '0');
      end case;
    end if;
end process;

There are a few answers on here that give an example of synthesizing case statements, (like this one), but they do not give any detail about how many LUTs are used.

I would like to know how to judge how many additional LUTs will be added if I add another when statement.

Klik
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  • Have you looked at the synthesized design at all? This is normally the best way to understand how the code is being implemented. – scary_jeff Aug 03 '16 at 07:55

1 Answers1

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The only way is to try it and see, in the FPGA technology you need.

A general answer would be "a few extra LUTs and FFs" (maybe tens) for each additional clause, but occasionally you stumble across a less-than-optimal synthesis tool behaviour that adds many more.

There's no magic involved, a good synthesis tool will add about as many gates as you would by expanding boolean expressions, simplifying the Karnaugh maps and drawing out the logic by hand. Only, in seconds instead of hours...

Since bus_addr is likely to be sparse (here, 4092 unused addresses) I strongly recommend a "when others" clause to define behaviour for unknown addresses. It can be as simple as

when others     => 
                   rd_data <= (others => '-');

i.e. don't cares, giving synthesis permission to do anything it wants, to optimise the logic size. Try (others => '0') for cleaner behaviour, and compare the resulting size.

You can also simplify these case arms, for example to

when RX_CTRL    => 
                   rd_data <= (31 =>rx_enable, 30=> rx_allow_tcp, others => '0');

Shouldn't affect the logic generated at all.

  • I will synthesize this and see for myself. I thought there might be a general equation or rule of thumb. For example, if I put 4000 when statements then I must be beyond the routing capabilities of the FPGA or it might make timing very difficult to be met. Is there a good way to estimate these limits with general rules, best practices, or an equation? – Klik Aug 03 '16 at 13:23
  • Any general equation fails when the tools can detect optimisations (such as, all cases except one set the lowest 29 bits to '0'). And, different FPGAs give different results. Synthesise blocks as you go, and you'll build a feel for it, or a "rule of thumb" if you like. –  Aug 03 '16 at 13:30