I am using a case statement in VHDL where the expression is a 12 bit bus address and the output is a 32 bit data bus.
Here is my code:
process (iAPB_BUS_IN.pclk)
begin
if rising_edge(iAPB_BUS_IN.pclk) then
if (write_pulse = '1') then
case bus_addr is
when TX_CTRL =>
rd_data(31) <= tx_enable;
rd_data(30) <= arb_suppress_mgmt;
rd_data(29) <= arb_suppress_2022;
rd_data(28 downto 0) <= (others => '0');
when TX_STATUS =>
rd_data(31 downto QUEUE_NUMBER) <= (others => '0');
rd_data(QUEUE_NUMBER -1 downto 0) <= tx_que_avalb;
when RX_CTRL =>
rd_data(31) <= rx_enable;
rd_data(30) <= rx_allow_tcp;
rd_data(29 downto 0) <= (others => '0');
--------------------------------------------------
-- What happens if I add another expression below?
--------------------------------------------------
when RX_CTRL2 =>
rd_data(31) <= rx_que;
rd_data(30) <= rx_allow_udp;
rd_data(29 downto 0) <= (others => '0');
end case;
end if;
end process;
There are a few answers on here that give an example of synthesizing case statements, (like this one), but they do not give any detail about how many LUTs are used.
I would like to know how to judge how many additional LUTs will be added if I add another when statement.