How to translate analog inputs at [-15,+15V] to [0,+3.3V] without ±15V rails?

Question

Title says it all, but to provide some context: the goal here is to design a 12-channels ADC system. Input signals varies between -15 and +15V. The acquisition system will probably be a mid/large arduino, but this is not a constraint.

Constraints:

• High input impedance (downscaling through resistor networks is excluded)

• Small footprint (once 12x count taken into consideration), low part count. Trying to keep this as simple as possible to assemble for a hobbyist

• Only supplies currently present: +3.3V (microcontroller), +5V (USB charger), +12-14V "automotive", non-regulated.

• Using an 12-to-1 I2C multiplexer as a first stage is an option, and this could free a lot of space, but this is not my preferred option

Exotic ICs easily sourced from major suppliers are fair game.

Goal is ~20 acquisitions per second, with acquisitions on the various channels as synchronous as possible. Accuracy requirement is low: +/- 50mV (on source) would do, in line with an 10-12bit ADC.

I've tried weird configurations with op-amp in summing configuration, but I'm out of ideas.

Thanks

Answer 1

This is a fun problem, but thankfully, you aren't the first person to run into this. High-speed ADCs tend to be picky about input drive, and high-speed ADC drivers are often made in low voltage processes, which means that accepting a high-voltage input requires some gymnastics, for which resistor dividers aren't an option due to high-speed impedance control issues. Instead, fully differential amplifiers can be used as attenuators, even for input signals that would be by themselves be outside the input CMVR of the fully differential amplifier.

Based on the procedures from these two appnotes -- we wind up with a circuit topology that looks like:

^{simulate this circuit – Schematic created using CircuitLab}

In this circuit, U1, C1, C2, and R1-R5 form a single-ended "differential" attenuator with a very high input impedance (set by R3 & R4 = 10MΩ) and a V/V of 1/10 set by the R1/R3 & R2/R4 ratio-pair of 1 to 10. R5 (Rt in the appnote) controls U1's noise gain to 2 to maintain stability as per the formula $$R_f = R_g \parallel \frac{R_t}{2},$$ C1 provides local decoupling for U1, and C2 keeps RFI out of the high-impedance input, forming a corner of about 8Hz with R3 to keep the Nyquist bandwidth below your 20SPS sample rate.

The THS4531A fully differential amp chosen is available for roughly $3 in singleton quantities in an easy-to-solder 8-pin SOIC, and provides very low input bias current and power draw, as well as input and output common mode ranges down to V-. R1-R5 must be 1% or better chip resistors (1% thick film is OK, but if you can get better tolerance/matching cheaply, do it) and C2 must be a stable (film, C0G) capacitor -- the THS4531A is a fast part (GBW of 36MHz) and will happily stuff RFI into your ADC all day long if you aren't careful with layout and decoupling/filtering.

The circuitry in the dashed box, namely U2 and C3-C5, provides a stable 1.65V reference for the common mode supply to U1 -- it can be shared across all channels, and also supplies a stable 3.3V reference that can be fed to the ADC Vref (instead of using the presumably noisy logic supply). The REF2033 is about $3.50 or so in onesies, and comes in a mildly tricky SOT-23-5 package; if a regular SOT-23 is preferred or the REF2033 proves too costly, the ISL21080-1.5 can be used instead to drop a couple bucks from the BoM -- C5 is omitted in that case, C3 becomes a 2.2nF (film or C0G) cap as the ISL21080's micropower output stage can't drive 100nF stably, and the 3.3V reference output is no longer available. Using the 1.5V reference also puts the output range at 0-3V instead of the 150mV-3.15V range provided by the depicted circuit; the latter provides more linear performance from the THS4531A at the low end of the output range, and also avoids any low-end nonlinearities in whatever ADC you're using.

Answer 2

Although the OP says no resistor divider networks, in a comment he says he aims to reproduce the capabilities of a cheapo multimeter. These have typically 10Mohm input resistance (though you can find 1Mohm if you go really cheap).

So, to get +/- 15v down to 0/3.3v with 10Mohm input, you could use this 10:1 divider

^{simulate this circuit – Schematic created using CircuitLab}

The input resistance is somewhere between 10 and 11Mohms, depending on the input resistance of your ADC.

The output resistance is between 1M and 1.1Mohm, depending on the resistance of the point you are measuring.

You say you want 20 readings per second, which is one every 50mS. If we want the reading to 'fully' settle (say 5 time constants) following a step change on the input, then the capacitive load that this divider drives must be limited to 10nF, which will give a maximum time constant of 10mS. No loads will accidentally have this much capacitance on their input, only filters. If you want a low pass filter on the input, then 10nF will not impact the dynamics at 20 readings per second, larger capacitors will give better filtering and slower response.

Some ADCs can cope with a 1Mohm input resistance as is, some can cope with this input resistance if they have a capacitor to ground to cope with current spikes (10nF is usually plenty), and some will require a much lower resistance source. If the last one is the case, then follow this divider with a buffer amplifier. As you have no negative rails, this will need to be at least a 'driving to ground' opamp like say LM324 (very cheap) operating between +12v and ground, or a low voltage rail to rail amplifier operating from +3.3v, like MC33202, 75p for a dual from CPC.