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Idea:

Run a 68000 emulator on a PC, and connect the PC to an existing 68000 system, replacing the CPU with a ribbon cable going to the PC.

I realize the emulation would not be cycle exact, but that is not the goal.

Question: how much would it take in terms of glue logic between the systems, minimum?

I have some crazy ideas: IDE port on PC is 5 volts. IDE is basically a 16 bit parallel port. The 68000 has 16 bits data bus. Maybe some latch to keep the 20 bit memory address? Reset flanks could be stored in and read out by emulator?

Prof. Falken
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    You could probably fairly easily probe the target system's response to CPU-generated addresses to see if the right chips are selected this way. Actually running the system would likely be much more difficult. – JustJeff Jan 07 '12 at 13:43
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    The method that used to be used for this is called an [ICE](http://en.wikipedia.org/wiki/In-circuit_emulator) – Kortuk Jan 07 '12 at 14:13

4 Answers4

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Get a PCI style FPGA board that you can use generic IOs for the target 68000 connection. Implement your control system in the FPGA, and write software to tell it what to do. That's basically making your own ICE kit. If the commercial ICE kits are horrendously expensive (check and find out if they are, I don't know), then this could potentially come in cheaper, and give you control over how it works. Check out Raggedstone, Broaddown or Mini-Can FPGA boards, they are relatively inexpensive boards, but not sure if it has enough accessible IO pins for what you need. Then check OpenCores for open-sourced PCI blocks and other things that may be useful. You may also need to add some level shifting stuff on a small PCB addon to these boards. Look up Xilinx/Altera white papers on using Quickswitches between 3.3V FPGA and 5V PCI, hooking the other connections to a 5V 68000 socket would be essentially the same process.

As I remember, the DIP 68000 is 68 pins, and some of those are not used in some systems, such as Amiga does not recommend using some of the 6800 style peripheral pins, and they become disconnected in later Amiga systems.

Prof. Falken
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billt
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  • With the last paragraph, you say that I don't have to care about implementing the 6800 style pins? – Prof. Falken Jan 09 '12 at 21:13
  • the plastic DIP package was 64 pins. there are also other form factors, but the OP didn't spec. – JustJeff Jan 09 '12 at 22:28
  • Commercial ICE kits are generally horrendously expensive, but depending on the specific 68000 model and packaging used, an old ICE may be available very inexpensively. I worked on a SEGA Genesis game in 1993 and we used an ICE that was US$10-15,000 at the time; 20+ years later, if you could find the same model, I expect it'd be pretty cheap... – Chris Hanson Dec 24 '14 at 07:46
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I would imagine this would be nigh on impossible to do.

Firstly, timing is critical in a CPU.

The CPU, while the master "device" in the system, is not the absolute master of all.

It is slave to the system clock.

Your PC and it's interface, and the emulator, would all be required to be slave to this master clock.

The IDE interface certainly couldn't do that.

You would need a specifically built interface which would do all the emulating of all the signals and control lines (which are all timing critical), as well as provide all the data and address lines (and there's a lot of them). With that it might be possible to do it, but it would be hard and expensive. Better to just emulate the whole system in total or use a real 68000 chip.

Majenko
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    Right. A system consisting of a simple prism of ROM, static RAM, and maybe parallel port might be ok, but any number of 'interesting' components are going to have critical timing. Keeping up with a UART could be tough. Keeping up with a disk controller would definitely be tough. Some (cheap) designs relied on the CPU for dynamic RAM refresh. DMA channels would probably be a show stopper. And basically anything that that throws an interrupt. – JustJeff Jan 07 '12 at 13:39
  • http://www.makestuff.eu/wordpress/?cat=18 seems to do what you suggested – Prof. Falken Jan 07 '12 at 13:53
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Depending on the system, you might or might not be able to fool the target hardware into 'thinking' it had a 68K present. In some (most) systems, as Majenko said, you'd need to respond to certain signals in real time, which would be a pain. However, if the target hardware doesn't have multiple bus masters, you might be able get away with it. You'd have to really investigate the timing requirements of the system in question. If it can handle being run at extremely low clock rates, or allows the clock to be suspended and restarted, the outlook is more hopeful.

But there are two other problems here.

One is, you don't want to connect the target hardware's data bus directly to your PC's IDE bus. The target should only drive data onto the PC's data bus when the PC wants it to, so you'd need a bidirectional buffer, decoded to respond to a suitable address in the PC's memory map. You correctly intuited that you'd need a buffer to capture data from the PC for the target address bus.

The other, and probably bigger pain, would be configuring the PC software to support this. You'd have to allocate at least a couple of addresses in the PC memory or I/O maps to access this target system adapter, and with modern operating systems, this doesn't happen without a device driver. So if you want to pursue this, you either need to know how to do that, or be prepared to learn it.

JustJeff
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  • http://hackaday.com/2011/02/03/stk200-pocket-change-programmer/ <-- demonstrates how to fool the parallel port driver to point to the IDE port, in Linux. :-) – Prof. Falken Jan 07 '12 at 14:40
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Actually what you are describing is quite close to an in-circuit emulator (ICE). For most popular chips like the 68000 you will find generally you can buy an ICE like this one for the 68000.

Since an ICE needs a way to interact with the user in addition to the target circuit board, a PC is often used for that purpose. One cable from the ICE will plug into the circuit board in lieu of the CPU chip and another will connect to the PC.

While perhaps going beyond the scope of your question, it is interesting to note that when a new CPU chip is being designed it will generally be simulated in software on some other existing computer first and then an ICE will be built with actual chip production being the last step. This is because it is much cheaper to make an ICE than to produce a complicated CPU chip the first time.

JonnyBoats
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