Loop for two binary values in VHDL

Question

I'm trying to write a loop for two binary values that repeat periodically at a specific amount of time that goes indefinitely or until a certain condition is met.

Here is what I have wrote (below), but the error states that I should be using the 'wait' statement with 'until' but when I use that then it says that the Boolean expression is used incorrectly.

This leads me to believe I'm using the loop wrong or doing something else wrong that I can't figure out.

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity moove is 
    port (clk : in std_logic;
        rst : in std_logic;
        count : out unsigned (7 downto 0));
end entity;

architecture moving of moove is
    constant period : time := 19.5 ms;
    constant cycles : integer := 120000; 
begin
    forwrd: process (clk)
    begin
        if rising_edge(clk) then 
            if rst = '1' then
                count <= "00000000";
            elsif rst = '0' then
                for i in 1 to cycles loop
                    count <= "01100100";
                    wait for period;
                    count <= "10010110";
                    wait for period;
                end loop;
            end if;
        end if;
    end process;
end architecture;

Are you trying to simulate this code or synthesize it? `wait for ...` statements are not synthesizable. — Dave Tweed, Jun 21 '16 at 11:11
If you will synthesize it you need to use a separate timer for the period of the signal instead of wait — Claudio Avi Chami, Jun 21 '16 at 11:30
Do you mean a counter, that will count to a specific value (time) and then i would load my binary value to the signal? — Serge, Jun 21 '16 at 11:37
@Serge "wait for" is used for the test bench that validates your logic. I do not think you can use them directly in your architecture. Just increment your "count" until some value and then reset it. — Nazar, Jun 21 '16 at 12:03
@Naz 'count' needs to be a constant value, i made a counter now and simulating now, since i need it to be over 40ms it will tale a little while — Serge, Jun 21 '16 at 12:13
Create a new value and increment it until it is equal to "Count" then reset. You need to know your clock period. So, then your constant count=40ms/clock period. — Nazar, Jun 21 '16 at 12:18
Yes, you're right, but how can i initiate reset to '1' and then to '0' without introducing a delay to the initiation of the next value of 'count' further down the line? — Serge, Jun 21 '16 at 12:51
Just realized I cant use reset as it is the main reset for the rest of the design — Serge, Jun 21 '16 at 13:25
I tried your way Naz, but the counter is the only way that works well. Thanks Claudio, not sure how to mark it as the right answer :/ — Serge, Jun 21 '16 at 14:11
It was a comment... Doesn't matter @Serge, the important thing is that you solved it and provided the answer — Claudio Avi Chami, Jun 22 '16 at 04:41

score 1 · Answer 1 · answered Jun 21 '16 at 17:53

Here is the working version. I'm using 100kHz clock.

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;


entity moove is 
port (clk : in std_logic;
        rst : in std_logic;
        count : out unsigned (7 downto 0));
end entity;

architecture moving of moove is
    signal Cnt: std_logic_vector(11 downto 0);
begin
forwrd: process (clk)
    begin
    if Rst = '1' then 
        Cnt <= (others => '0');
            elsif (rising_edge(Clk))then
            Cnt <= Cnt +1;  
            if (Cnt = "011111010000") then--20ms(2000 clock cycles)
            count <= "10010110";--1.5ms
            elsif (Cnt = "111110100001") then
            Cnt <= "000000000000";
            count <= "01100100";--1ms

end if;
end if;
end process;
end architecture;

Loop for two binary values in VHDL

1 Answers1