I've been learning about ACF for doing a chip-on-board application, but I'm having a little trouble finding enough information about it. My main questions are:
You already know this, but I am repeating it in case someone stumbles across this. ACF's property that makes it so appealing is it's anisotropy. Ideally, it is highly conductive in the direction of the z axis, while insulating in the x-y plane.
This is not sorcery, but very cool material science/engineering. The ACF itself is a matrix of insulated polymer spheres with a small shell of nickel and gold, covered in insulation. These spheres are tens of µm across. They can be squished with pressure, making them turn into an oval shape. This rips apart the insulating layer, baring the Au coating, which will cold weld to adjacent and likewise bared Au surfaces. The epoxy is hardened by the same heat used to produce this pressure some seconds later, and the chip is now electrically bonded. ACF is not very mechanically robust however, so usually some potting material (a resin etc.) is put around the periphery of the die to secure it in a more robust way.
How is alignment done for very fine pitch chips?
Very carefully. And by a machine.
ACF allows bonding of unsolderably small pitches (due to surface interactions, not simply being really tiny - even very wee 1mm tall engineers with even wee-er soldering irons or paste syringes could do no better - it's a limitation due to the physical properties of solders), pad sizes of 50µm x 50µm and 10µm gaps are typical. A 10µm gap is unsolderable, enough solder to prevent voiding will overhang the pad enough to form a bridge over 10µm. Even with larger gaps, even slight misalignment of 10 µm results in much higher chances of shorted pads and open pads vs 5µm alignment. The ACF itself can be slapped on by hand, it just needs to cover all the places you want to bond. But a vision system is required to actually orient the chip, using either the reflections of pads at the periphery (ACF is transparent) or fiducial markers. 2µm alignment error is fairly standard.
To be clear, there is no self-alignment mechanism that has been holding our hands (and our chips) like there is with solder. Solder's surface tension is absolutely ridiculous. It will physically drag a TO-247 across the board if it wants to. This, combined with very selective wetting, basically make all but the sloppiest alignment a non-issue. ACF is as unforgiving as solder processes are forgiving. Humans can pretend they can work on small stuff largely thanks to the self-alignment of solder, but ACF alignment is simply out of our league. Alignment is done by a machine.
The whole point of ACF was that it work with existing equipment, so any vision system used to align fine pitch components on a substrate will work just fine for ACF. No special alignment machine is needed. Special meaning different than any vision system. A vision system is unquestionably required.
Are there guidelines to follow for how large to make the footprint pad for each connection
Geometry is more important than size. You want to maximize pad area while also maximizing the gap between pads. How you go about this is going to depend on the actual footprint geometry.
The probability of an open connection is inversely dependent on pad area, so larger pads are better. But the probability of two pads shorting together is likewise inversely dependent on how wide the gap is between pads. The wider the gap, the more spheres will be needed to bridge that horizontal gap, and it quickly becomes less and less likely. This is another reason alignment is so critical - even slight misalignment can increase the odds of a short and non-linearly.
If your footprint allows, the shape that will give you the most area but also the most gap between them is a rectangle. Narrow in the pin to pin direction, so there is as much gap as reasonable between adjacent pins, but long in the other direction to give more contact area. Generally, the pad also needs to be similar in size and shape to the thing to be bonded, so there is not a huge amount of room to play with the pad size or shape anyway. But within the bounds placed upon you, maximum area and maximum gap are what you always want to go for.
Does the die have to be manufactured specifically for ACF application? Are solder bumps required?
Yes and no. Solder bumps cannot be bonded using ACF. ACF bonds gold to gold surfaces only, so your carrier must use ENIG, and the chip must have gold bumps. If a chip has solder bumps, it cannot be used with ACF.
The chip must have metal gold bumps on each pad, and while some chips may be manufactured to include them, it is certainly not required. Again, the power with ACF is that it can be used with already available process equipment. In this case, any chip that can be wire bonded or has wire-bondable pads can be used for ACF. You create the gold bumps on each pad with any available gold wire bonding equipment with the necessary tolerances. A gold wire is bonded to the pad as normal, but the wire is immediately cut, leaving only the gold bead /bump that results from the bonding process of the wire to pad. So it's actually significantly simpler, easier, quicker, and cheaper than real wire bonding, as you're just wire bumping each pad.
After doing this, the chip is completely prepared for ACF bonding. Make sure the surfaces are clean, align, heat, and you're done. This allows the highest flexibility and is one of the stronger points that makes ACF so attractive. Being able to use equipment they already have makes people very happy. Or at least less grumpy.
One final note: I suspect that very process interoperability is the reason you may be having so much trouble finding information. Most facets of ACF processes are simply the same processes already in use. Alignment is done no differently than anything else, only a strip of ACF is stuck to the board before hand. In general, ACF is easier and simpler than any alternative, and most of the meat and potatoes is in controlling the properties of the ACF you're using. For example, you will generally use an ACF with a ball size that is sized specifically for the pad area you are using. It is ultimately a stochastic process, so you just need to keep the probability of opens and shorts acceptably low, and beyond that, it is hard to screw up. There is no excess to clean, no flux, it all just sets and hopefully is only conductive in the spots you want it to be.
I can only speak to this from my experience with RFID ICs using GF (formerly IBMs) 8RF process. There's a few items that change on frequency and substrate, but if you are going to make a 900MHz tag on a paper substrate, these are the sorts of things you'll see:
The alignment usually does not need to be perfect because the bumps sit onto the antenna so you have extra space, and usually 2-4 pins only.
The C4 bumps are 120uM, so if you are going to put these on a non-flexible board, you use something similar to board via as a contact point. On a flexible board, I've never seen high densities; however, I would assume that it would have the same constraints as a rigid board where you have a 0,0 point, that then has the ability to place a component to 50uM resolution.
I do not believe so, unless you have space constraints due to #2. The C4 bump grid can be very dense, so I would expect that you would have to remove some density for a flexible substrate. To my knowledge, solder bumps are required; however, I have taken a wire-bond IC with the pad ring, and then flowed solder on it and then reflowed it. (it's easier to get my probes on a pad than a ball)
I would assume that someone who makes the flexible substrates would have a "check list" for density and spacing in the DRC (design rule check) list. You might be able to just ask for this, and then match things up with bare dies that are available that might work for your application.
