verilog state machine - state won't update

Question

So I'm trying to simulate a state machine with outputs s and v and a state. for some reason our s and v values are updating but the state refuses to change, any help would be awesome

module controller(
  input x,
  input clk,
  output reg S,
  output reg V);

  parameter  S0 = 3'b000, S1 = 3'b010, S2 = 3'b001, S3 = 3'b101, S4 = 3'b011, S5 = 3'b100,S6=3'b111;

  reg [2:0] state = S0; //assuming starting at S0

  always @(negedge clk) 
    case(state)
      S0: begin
        if(x==0)begin
          S<=1;
          V<=0;
          state<=S1;
        end else begin
          S<=0;
          V<=0;
          state<=S2;
        end
      end
      S1:begin
        if(x==0)begin
          S<=1;
          V<=0;
          state<=S3;
        end else begin
          S<=0;
          V<=0;
          state<=S4;
        end
      end
      S2: begin
        if(x==0)begin
          S<=0;
          V<=0;
          state<=S4;
        end else begin
          S<=1;
          V<=0;
          state<=S4;
        end
      end
      S3: begin
        if(x==0)begin
          S<=0;
          V<=0;
          state<=S5;
        end else begin
          S<=1;
          V<=0;
          state<=S5;
        end
      end
      S4:begin
        if(x==0)begin
          S<=1;
          V<=0;
          state<=S5;
        end else begin
          S<=0;
          V<=0;
          state<=S6;
        end
      end
      S5: begin
        if(x==0)begin
          S<=0;
          V<=0;
          state<=S0;
        end else begin
          S<=1;
          V<=0;
          state<=S0;
        end
      end
      S6: begin
        if(x==0)begin
          S<=1;
          V<=0;
          state<=S0;
        end else begin
          S<=0;
          V<=1;
          state<=S0;
        end
      end
    endcase

endmodule


`timescale 1ns/1ps
module driver();
  wire testX,testClk, testS,testV;

  controller c
  (
    .x (testX),
    .clk (testClk),
    .S (testS),
    .V (testV)
  );

  tester t
  (
    .x (testX),
    .clk (testClk)
  );

endmodule

`timescale 1ns/1ps
module tester(
  output reg x,
  output reg clk
);

  always
    begin
      clk <=0;
      #5;
      clk <=1;
      #5;
    end

  initial
    begin
      //1011 1100 1101
      #2.5 x=1;
      #10 x=0;
      #10 x=1;
      #10 x=1;
      #10 x=0;
      #10 x=0;
      #10 x=1;
      #10 x=1;
      #10 x=1;
      #10 x=1;
      #10 x=0;
      #10 x=1;
    end 

endmodule

I ran your code in 4 different simulators on [EDAplayground](http://edaplayground.com), and `state` is being updated — Greg, Apr 10 '16 at 00:40
thank! (sorry about the delayed response) i think there was something just getting messed up. copy pasted the file in a new project and it worked fine — greenteam, Apr 28 '16 at 22:25

score 1 · Answer 1 · answered Apr 20 '16 at 13:40

The problem is that you don't have any reset signal

It is unusual to initialize a register with the folowing code line :

reg [2:0] state = S0; //assuming starting at S0

1.Change it into :

reg [2:0] state;

2 Add a real Reset Signal input :

input reset, 3. Use this reset signal (active high) to initialize your state register:

module controller(
  input x,
  input clk,
  input reset,
  output reg S,
  output reg V);

  parameter  S0 = 3'b000, S1 = 3'b010, S2 = 3'b001, S3 = 3'b101, S4 = 3'b011, S5 = 3'b100,S6=3'b111;

  reg [2:0] state ;

always @(negedge clk or posedge reset) begin
  if (reset) begin
    state <= 0;
    S <= 1;
    V <= 0;
  end
  else begin
    case(state)
      S0: begin
        if(x==0)begin
          S<=1;
          V<=0;
          state<=S1;
        end else begin
          S<=0;
          V<=0;
          state<=S2;
        end
      end
    .......
      S6: begin
        if(x==0)begin
          S<=1;
          V<=0;
          state<=S0;
        end else begin
          S<=0;
          V<=1;
          state<=S0;
        end
      end
    endcase
 end
endmodule

....

score 0 · Answer 2 · answered Apr 25 '16 at 15:21

0

The above code is working fine. You should probably check your simulator settings. Also it is good practice to have a reset signal as all practical machines/systems have a reset option. The reset is usually 'active low'.

answered Apr 25 '16 at 15:21

Hesham Ahmad

21
1

verilog state machine - state won't update

2 Answers2