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I have one solved problem, My teacher solved it as follows:

enter image description here

and says

with B=C=D=1 for change value of 'A' from one to zero we have Static-Hazard '1'.

but I think we should say

with B=C=D=1 for any change values of 'A' we have Static-Hazard '1'.

Which one is Correct? Any idea?

Scott Seidman
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Davied Zuhraph
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2 Answers2

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Your teacher is correct, if there is a propagation delay for NOT gates going into the NAND gates. If there is no propagation delay for NOT gates going into the NAND gates, then there would be no Static-Hazard '1'.

Assuming there will be a propagation delay for NOT gates going into the NAND gate, there will only be a Static-Hazard '1' when 'A' goes from 1 to 0. There is not another Static-Hazard '1' when 'A' goes from 0 to 1.

To demonstrate this, I recreated the circuit using VHDL and simulated it.

At 10 ns time in the waveform, you can see 'A' transitions from 0 to 1. However, the output 'F' does not change. At 20 ns, 'A' transitions from 1 to 0. After 1 ns (a propagation delay I programmed all components to have), 'F' changes from 1 to 0 and stays at 0 for 1 ns. After that 1 ns, it changes back to 1. This is an example of Static-Hazard '1'.

VHDL Code: https://gist.github.com/pjbollinger/55e021b6f560fbedac10

Waveform Result:

Waveform Result

pjbollinger
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  • If we reduce this circuit with the static values of B, C and D equal 1. we get a circuit that is symmetric for A and negated A. F = not (A and not A) So there is a probability of having a static 1 hazard for any change of A. isnt it? – user4249446 Mar 14 '16 at 12:43
  • @user4249446 I understand what you are saying. Let's assume it takes 1 tick to propagate through the NOT gate and the NAND gate. `At start, A = 1 and F = 1` `1 tick, A = 0` `2 tick, the output of A' is switching to 1, but A is already 0 so F remains at 1` `Final state, A = 0 and F = 1.` Let's do the same thing but starting with A = 0. `At start, A = 0 and F = 1` `1 tick, A = 1.` `2 tick, the output of A' is switching to 0, but A is already 1 so F changes to 0` `3 tick, the output of A' is now 0 and A is still 1, so F changes to 1` `Final state, A = 0 and F = 1` – pjbollinger Mar 14 '16 at 17:32
  • so what is the last conclusion? my fact is right or teacher? – user4249446 Mar 14 '16 at 17:59
  • Sorry, the conclusion is the teacher is correct. The static 1 hazard will only occur when A goes from 1 to 0. It does not occur when A goes from 0 to 1. – pjbollinger Mar 14 '16 at 18:20
  • you have an error in your code, you are not implementing the logic in the question. – user4249446 Mar 14 '16 at 18:28
  • Can you tell me which line has the error and describe why it's incorrect? – pjbollinger Mar 14 '16 at 18:34
  • Let us [continue this discussion in chat](http://chat.stackexchange.com/rooms/36977/discussion-between-pjbollinger-and-user4249446). – pjbollinger Mar 14 '16 at 19:25
  • Your code implements not A and not C in the first nand gate instead of not A and C and the second nand gate implements not A and B instead of not A and not B. This error will not change the behavior of the static hazard. What is it that you code will prove? If you simulate this you will probably only see the hazard for one of the transitions of A. A hazard is an artifact of different physical delays through the circuit, this artifact will not show up in an event driven simulation like modelsim. – user4249446 Mar 14 '16 at 19:34
  • Thanks for pointing out the error. Like you said though, it will not change the behavior of this static hazard. This code proves that the hazard will only occur during A transition from 1 to 0. I added time delays to the code to simulate physical delays. Your statement will be true IF there is no propagation delay when using a NOT gate. Good questions for your teacher would be, "What are the propagation delays for a NOT gate and NAND gate? Is there a delay between the inverted inputs in comparison to the non-inverted inputs?" – pjbollinger Mar 14 '16 at 20:07
  • please update your answer. I think this question is so tricky and all aspect of answer should be provided. would you please update your answer with this tips. – user4249446 Mar 14 '16 at 21:17
  • would you please consider "no propagation delay when using a NOT gate" in your answer – user4249446 Mar 17 '16 at 15:48
  • I have expanded my answer to include "no propagation delay for NOT gates". After some thought, I have determined there would be no Static Hazard. If NOT gates have no propagation delay, then the only way a static hazard can form is if the 3-input NAND gate has a different propagation delay compared to the 2-input NAND gate. – pjbollinger Mar 17 '16 at 16:39
  • Oh, OK. That is also a pretty good answer. It assumes the input has no delay, but the NAND gates do have a delay. – pjbollinger Mar 17 '16 at 17:29
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The answer is that there is not enough information in the question to decide between the two possibilities.

If you assume that \$\overline{A}\$ is generated by an inverter fed from \$A\$, that the gates have the same propogation delay as each other and the same propagation delay under all conditions then your teacher is right.

When \$A\$ goes from 0 to 1, \$A\$ and \$\overline{A}\$ will both briefly be 1 at the same time, the output of the first level gates will therefore always contain at least one zero and there will be no glitch in the final output.

On the other hand when A goes from 1 to 0, \$A\$ and \$\overline{A}\$ will both briefly be 0 at the same time causing all three of the first stage gates to briefly output a 1 at the same time causing a glitch in the final output.

But those are IMO unwarranted assumptions. Propagation delays vary between gates, between different inputs on the same gate and with the direction of the transition. Depending on how other logic in the system is designed \$A\$ may in fact be generated from \$\overline{A}\$ rather than vice versa.

In the more general case where signals arriving on different paths could arrive in any order there could be a glitch in either direction (or if you get really unlucky a glitch in both directions).

Peter Green
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