AVR external interrupt triggering by the falling edge: for how long should I keep signal low to guarantee triggering?

Question

The question header appeared to bee too long. I'm sorry for that.

So I have a schematic generating a short LOW on INT0 pin of ATmega48PA. From the simulation I figured out that the LOW level will be there for about 800 ns. I plan to clock the AVR from internal RC with 1:8 divider which means 1 MHz Fosc.

How do I make sure that the interrupt will be triggered?

I make some reading of the datasheet but I was looking in a wrong chapters or there is no such information.

Could you please point me into the right direction to find needed info?

Thank you!

score 6 · Accepted Answer · answered Feb 26 '16 at 17:46

6

From the datasheet, for the description of ISC11, ISC10:

If edge or toggle interrupt is selected, pulses that last longer than one clock period will generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If low level interrupt is selected, the low level must be held until the completion of the currently executing instruction to generate an interrupt.

Since a 1MHz clock means that the 800ns interrupt pulse will last less than 1 cycle, the interrupt will not be generated reliably. The longest AVR instruction requires 4 cycles, so using a minimum clock of 6MHz will ensure that you catch all interrupts while the chip is active.

answered Feb 26 '16 at 17:46

Ignacio Vazquez-Abrams

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As I understand from the quotation edge triggering interrupt not requiring instruction to be executed. So I'd say that in my particular case I will need to increase the low level for 1000 ns to guarantee the interrupt. Right? – Roman Matveev Feb 26 '16 at 18:03
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If you switch to falling-edge triggering, yes. – Ignacio Vazquez-Abrams Feb 26 '16 at 18:04

AVR external interrupt triggering by the falling edge: for how long should I keep signal low to guarantee triggering?

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