When is using latches better than flip-flops in an FPGA that supports both?

Question

The Question:

When is using latches better than flip-flops in an FPGA that supports both?

Background:

It is a well-known principle that level-sensitive transparent latches should be avoided in FPGAs, and edge-sensitive flip-flops should be used exclusively. Most FPGA architectures natively support both latches and flip-flops.

The general advice -- even from the FPGA vendors -- is to watch out for latches, or never use latches, etc. There are very good reasons for this advice, the details of which is all well-known. However, most advice is phrased, "don't use latches unless you know you need them".

I am an experienced FPGA designer, and over the years every time I thought I knew that I needed a latch, a quickly realized that there was a better way to do it with flip-flops. I am interested in hearing examples of when using latches is unequivocally better.

Important Note:

Latches vs. flip-flops often gets people riled up. I am only interested in the answer to the question. Responses explaining the difference between latches and flip-flops, expounding reasons to use NOT use latches, detailing why flip-flops are better than latches, talking about how latches are better in non-FPGA targets, etc, would be totally off-topic.

Answer 1

Your question is basically, "when do you know you need latches?" Which, as you implied, is a subjective question. Expect more opinion than fact as answers. That being said, here is my opinion:

I, like you, often find better ways to use flip-flops thus avoiding latches. The resulting logic is often more elegant and robust. But there are times where I don't have enough control over the logic to avoid latches. For example, I might be interfacing to a processor bus that requires latches to meet the desired specifications. Since I can't redesign the CPU or the bus, I'm stuck with the latch.

In the past 13+ years, that is the only time I have needed latches.

Answer 2

Flip flops are often preferable to latches because they have only four race conditions/constraints:

1. setup time between a change to the data input and a following active clock edge, and
2. hold time between a clock edge and the next change to the data input;
3. minimum active clock pulse duration;
4. minimum inactive clock pulse duration.

If those constraints are met, the output of a flip flop will be entirely "clean" and free of wonkiness. Further, the timing of a flip flop is in a sense "digital": provided timing constraints are met, the output will only change within a predictable window after an active clock edge, regardless of input timing. The effect of cascading flip flops is thus predictable, regardless of depth. By contrast, the timing of a latch output is much more "analog". A delay on the signal going into a latch can cause a delay in the signal coming out. Even if the latch's own constraints are met, this delay may cause problems downstream.

I would recommend using latches in cases where the required behavior of a chip's outputs may be most reasonably modeled by one. For example, one's hardware is supposed to behave as a serial-to-parallel converter where, between the rising and falling edges of the first clock following a frame sync, the first output tracks the input; between the rising and falling edges of the second clock, the second output tracks the input, etc. One could design a circuit using flip flops and purely combinatorial logic which would yield such behavior provided timing constraints were met, but such a circuit would be more complicated than one using latches, and would be more prone to behave oddly if timing constraints were not met.

Answer 3

In my work sometimes I had to implement latches in the FPGA, but it was always a "last resort" solution. Typical applications included connections with asynchronous interfaces or buses, if I could not assure a clock with speed sufficient to ensure proper sampling and synchronization of the bus and control signals.

The main problem is that the latch is an asynchronous block. Therefore you must ensure, that the combinational functions which generate input signals for the latch are race-free. Otherwise they may generate glitches, which may be latched, causing hazards in your system.

To avoid races, you have to implement these combinational function in a special reduntant way. Unfortunately (in this particular case ;-), otherwise it is a very good property) the FPGA synthesis tools optimize your design removing all redundancy. Therefore if you want to implement a latch in FPGA, you have to implement it "by hand", and protect against optimization (e.g. in VHDL you may need to set attribute "keep" to "true" for signals used internally in your latch).

Answer 4

In terms of timing:

If we are using flip flops in a design then the performance depends upon the longest combinational path delays.

if we use latches in place of flip flops we can compensate the longest combo path delays by borrowing time from the shorter path delays in the next stages. With this we can reduce the delays and increase performance of the design.